12_Memory.pdf

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Pamiİġ ulotna RAM

Pamiħę ulotna RAM Volatile R andom A ccess M emory)

Technika cyfrowa 2

utrata cc

ccc

wykĀad 12

SRAM c

c

c

cc

c

cc

Pamiħci procesorw

DRAM c

c

Katedra Metrologii Elektronicznej i Fotonicznej

Andrzej Stİpieĺ

Pamiİġ nieulotna NVRAM

Pamiİġ ROM (R ead -O nly M emory )

ccccc

ROM cccc

PROM Programmable ROM

c

EPROM Electrically Programmable ROM

c

OTP EPROM

EEPROM Erasable Electrically Programmable ROM

c

Flash EEPROM c

cc

Pamiħę nieulotna NVRAM N V R A cc M

zachowanie cc

ccc

cc

c

c c

cc

cc

c

cc

ccc

Memory Attributes

APPLICATION NOTE 63. Using Nonvolatile Static RAMs.

Dallas Semiconductor, Mar 29, 2001

Memory Parameter (www.st.com

Memories)

Memory Size c c c

ccc

Supply Voltage c

c

Memory Organization

Access Time

Chip Enable c

Output Enable

Programming Voltage Current

c c c

Standby Supply Voltage Current c

c c

Operating Temperature c

c

c

c

Static RAM +++

+ +++ +++

DRAM

+++

+++ ++ +++

PSEUDO

STATIC RAM +

+

++

+ +++

NV SRAM

+++ ++ + +++ +++ ++

Flash

++ ++ ++ ++ ++

+

++

EEPROM

+

++

+

+

+

+

EPROM

++ ++ ++ ++

+

++

OTP EPROM +++ +++ +++ +++ +

+++

ROM

+++ +++ +++ +++ +

+++

1

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Memory - Signal Names

Microprocessor

& Memory

V CC

V SS

V PP

A 0 .. A XX

D 0 .. D XX Q 0 .. Q XX

RD

WR

CS E

O E G

P

NC c

DU

c

ROM

Memory

Address Bus

Data Bus

Microprocessor

Microcontroller

RAM

Memory

Single CS SRAM & dual CS SRAM

Single CS SRAM & dual CS SRAM

TNAL9803. BENEFIT OF

DUAL CS. TECHNICAL

NOTE

SAMSUNG Electronics CO.,

LTD. 1998

TNAL9803. BENEFIT OF DUAL CS. TECHNICAL NOTE

SAMSUNG Electronics CO., LTD. 1998

cc

c

c ccc

c

c c

c

SRAM ( S tatic R andom A ccess M emory)

NV SRAM ( N on V olatile S tatic R andom A ccess M emory)

ccc

c

c

c

c c

c c

c

cccc

c cc

c

c cc

cc

c

cc

c

cc

c

c c cc

ccc

2

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SRAM

K6R1008V1D (1/4)

SRAM Single Access Read Cycle

K6R1008V1D.

1Mb Asynchronous

Fast SRAM High-Speed

CMOS Static RAM.

Samsung Electronics

June 2003

c

cc

t RC

c

t AA

t OH

???

SRAM - READ K6R1008V1D-08 (3/4)

SRAM K6R1008V1D-08/ -10 (2/4)

c

c

c

c

cc

c

cc

c

cc

c

SRAM - Write K6R1008V1D-08 (4/4)

Memory

& Memory (1/2)

K6R1008V1D. 1Mb Asynchronous Fast SRAM High-Speed CMOS

Static RAM. Samsung Electronics June 2003

K6F1008V2C. 128Kx8 bit Super Low Power and Low Voltage

CMOS Static RAM. Samsung Electronics, March 2005

c

m

c

( OE =Low Fixed)

(CS = Controlled)

c

cc

cc

3

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Memory

& Memory (2/2)

Synchronous Pipelined SRAM

K6R1008V1D. 1Mb Asynchronous Fast SRAM High-Speed CMOS

Static RAM. Samsung Electronics June 2003

K6F1008V2C. 128Kx8 bit Super Low Power and Low Voltage

CMOS Static RAM. Samsung Electronics, March 2005

K7P323688M / K7P321888M.

1Mx36 & 2Mx18 Synchronous Pipelined SRAM

SAMSUNG Electronics CO., LTD.

c

Pipeline cc

cc c

cc

ccc

cc

c

c

c

Flow-through cc

cc

cc

Synchronous Pi pelined S RA M Timing Waveforms of Normal

Active Cycles (G Controlled, SS=Low)

Synchronous Pipelined SRAM Functional Block Diagram

c

Read

Address

Register

>3,3ns

c

A1

A2

A3

A4

A5

A4

Write

Address

Register

c

c

Q1

Q2

D3

D4

Q5

Q4

c

c

D3, D4 c A3, A4

Q4 c

A4 ccc

c

c

Synchronous Pipelined SRAM IEEE 1149.1 Test Access Port &

Boundary SCAN-JTAG

DRAM ( D ynamic R andom A ccess M emory)

cc

c

cc

c

c

c

c

c c

c c

cc c c

c

c

cc c

c

cccc

4

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SRAM / DRAM Cell

DRAM Architecture

c

SRAM Cell

DRAM Cell

c

c

c

cc

cc

Memory

Array

C

ccc

cc c

c

1. Activation:

ccc

c

2. Access Column:

c

3. Precharge:

c

c

cc

DRAM - timing

What does 4-3-3 SDRAM mean

Engineer To Engineer. Note EE-126 Contributed by Robert Hoffmann,

European DSP Applications. Analog De vi ces, Rev1 (20-March-02)

t RP = 20 n s

4 Î 3 Î 3

CL = t CAC / t CLK = 3,33

4

c

t RP / t CLK = 2,67

3

t R CD = 20 ns

t RCD / t CLK = 2,67

3

t CAC = 25 ns

What does 2-3-3-6-1T DRAM mean

DRAM Refresh

Engineer To Engineer. Note EE-126 Contributed by Robert Hoffmann.

European DSP Applications. Analog Devices, Rev1 (20-March-02)

TN-04-30. VARIOUS METHODS OF DRAM REFRESH

Rev. 2/99, Micron Technology

t RAS = 40 ns

t RP = 20 n s

2 Î 3 Î 3 Î 6

CL = t CAC / t C LK = 2

2

c

t RP / t CLK = 2,67

3

ccc capacitor

20-40 fF ccc

c ccc c

t R CD = 20 ns

t RCD / t CLK = 2,67

3

t RAS / t CLK = 5,33

6

t CAC = 15 ns

Bank cycle time

DRAM refresh c c

c

Note: The Refresh uses internal read during t RAS and write during t RP .

Note: The Refresh row cycle t RC =t RAS +t RP .

3 refresh modes

5

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