mtp2955v.pdf

SEMICONDUCTOR TECHNICAL DATA

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by MTP2955V/D

P–Channel Enhancement–Mode Silicon Gate

TMOS POWER FET

12 AMPERES

60 VOLTS

R DS(on) = 0.230 OHM

TMOS V is a new technology designed to achieve an on–resis-

tance area product about one–half that of standard MOSFETs. This

new technology more than doubles the present cell density of our

50 and 60 volt TMOS devices. Just as with our TMOS E–FET

designs, TMOS V is designed to withstand high energy in the

avalanche and commutation modes. Designed for low voltage, high

speed switching applications in power supplies, converters and

power motor controls, these devices are particularly well suited for

bridge circuits where diode speed and commutating safe operating

areas are critical and offer additional safety margin against

unexpected voltage transients.

New Features of TMOS V

•

On–resistance Area Product about One–half that of Standard

MOSFETs with New Low Voltage, Low R DS(on) Technology

•

Faster Switching than E–FET Predecessors

Features Common to TMOS V and TMOS E–FETS

•

CASE 221A–09, Style 5

TO–220AB

Avalanche Energy Specified

•

I DSS and V DS(on) Specified at Elevated Temperature

•

Static Parameters are the Same for both TMOS V and TMOS E–FET

MAXIMUM RATINGS (T C = 25 ° C unless otherwise noted)

Rating

Symbol

Value

Unit

Drain–to–Source Voltage

V DSS

Vdc

Drain–to–Gate Voltage (R GS = 1.0 M W )

V DGR

Vdc

Gate–to–Source Voltage — Continuous

Gate–to–Source Voltage — Non–Repetitive (t p

V GS

V GSM

± 25

Vdc

Vpk

10 ms)

Drain Current — Continuous

Drain Current — Continuous @ 100 ° C

Drain Current — Single Pulse (t p 3 10 m s)

I D

I DM

8.0

Adc

Apk

Total Power Dissipation

Derate above 25 ° C

P D

0.40

Watts

Operating and Storage Temperature Range

T J , T stg

– 55 to 175

° C

Single Pulse Drain–to–Source Avalanche Energy — Starting T J = 25 ° C

(V DD = 25 Vdc, V GS = 10 Vdc, Peak I L = 12 Apk, L = 3.0 mH, R G = 25 W )

E AS

216

Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient

q JC

2.5

62.5

° C/W

q JA

° C

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit

curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

Designer’s, E–FET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Maximum Lead Temperature for Soldering Purposes, 1/8 , from case for 10 seconds

T L

260

REV 3

W Motorola, Inc. 1997

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS (T J = 25 ° C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

(Cpk

2.0) (3)

V (BR)DSS

(V GS = 0 Vdc, I D = 0.25 mAdc)

Temperature Coefficient (Positive)

—

Vdc

mV/ ° C

Zero Gate Voltage Drain Current

(V DS = 60 Vdc, V GS = 0 Vdc)

(V DS = 60 Vdc, V GS = 0 Vdc, T J = 150

I DSS

m Adc

—

100

Gate–Body Leakage Current (V GS =

15 Vdc, V DS = 0 Vdc)

I GSS

—

100

nAdc

ON CHARACTERISTICS (1)

Gate Threshold Voltage

(Cpk . 2.0) (3)

V GS(th)

(V DS = V GS , I D = 250 m Adc)

Threshold Temperature Coefficient (Negative)

2.0

—

2.8

5.0

4.0

—

Vdc

mV/

Static Drain–to–Source On–Resistance

(Cpk

1.5) (3)

R DS(on)

Ohm

(V GS = 10 Vdc, I D = 6.0 Adc)

—

0.185

0.230

Drain–to–Source On–Voltage

(V GS = 10 Vdc, I D = 12 Adc)

(V GS = 10 Vdc, I D = 6.0 Adc, T J = 150 ° C)

V DS(on)

Vdc

—

2.9

2.5

Forward Transconductance (V DS = 10 Vdc, I D = 6.0 Adc)

g FS

3.0

5.0

—

mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

C iss

—

550

700

(V DS = 25 Vdc, V GS = 0 Vdc,

f = 1.0 MHz)

25 Vdc V

0 Vdc

Output Capacitance

f = 1.0 MHz)

C oss

—

200

280

Reverse Transfer Capacitance

C rss

—

100

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time

t d(on)

—

Rise Time

(V DD = 30 Vdc, I D = 12 Adc,

V GS =10Vdc

30 Vd I

12 Ad

t r

—

100

V GS = 10 Vdc,

R G = 9.1 W )

Turn–Off Delay Time

t d(off)

—

)

Fall Time

t f

—

Gate Charge

Q T

—

Q 1

—

4.0

—

(V DS = 48 Vdc, I D = 12 Adc,

48 Vd I

12 Ad

( DS

V GS = 10 Vdc)

, D

Q 2

—

9.0

—

Q 3

—

7.0

—

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (1)

(I S = 12 Adc, V GS = 0 Vdc)

(I S = 12 Adc, V GS = 0 Vdc, T J = 150

V SD

Vdc

—

1.8

1.5

3.0

—

Reverse Recovery Time

t rr

—

115

—

t a

—

(I S = 12 Adc, V GS = 0 Vdc,

12 Ad V

0 Vd

( S

dI S /dt = 100 A/ m s)

, GS

t b

—

Reverse Recovery Stored Charge

Q RR

—

0.53

—

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the drain lead 0.25 , from package to center of die)

L D

—

4.5

—

Internal Source Inductance

(Measured from the source lead 0.25 , from package to source bond pad)

L S

—

7.5

—

(1) Pulse Test: Pulse Width 3 300 m s, Duty Cycle 3 2%.

(2) Switching characteristics are independent of operating junction temperature.

(3) Reflects typical values.

C pk =

Max limit – Typ

3 x SIGMA

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

V DS

10 V

T J = 25 ° C

V GS = 10 V

T J = – 55 ° C

9 V

8 V

100 ° C

25 ° C

7 V

6 V

5 V

V DS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)

V GS , GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics

Figure 2. Transfer Characteristics

0.40

0.250

0.35

V GS = 10 V

0.225

T J = 25 ° C

V GS = 10 V

0.30

T J = 100

0.200

0.25

0.175

0.20

25 ° C

0.150

15 V

0.15

–55

0.125

0.10

0.100

0.05

0.075

0.050

I D , DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Current

and Temperature

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

2.0

1000

V GS = 0 V

1.8

V GS = 10 V

I D = 6 A

1.6

1.4

T J = 125

1.2

1.0

100

0.8

0.6

0.4

0.2

– 25

100 125 150

175

T J , JUNCTION TEMPERATURE (

V DS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 5. On–Resistance Variation with

Temperature

Figure 6. Drain–To–Source Leakage

Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

–50

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge controlled.

The lengths of various switching intervals ( D t) are deter-

mined by how fast the FET input capacitance can be charged

by current from the generator.

The published capacitance data is difficult to use for calculat-

ing rise and fall because drain–gate capacitance varies

greatly with applied voltage. Accordingly, gate charge data is

used. In most cases, a satisfactory estimate of average input

current (I G(AV) ) can be made from a rudimentary analysis of

the drive circuit so that

t = Q/I G(AV)

During the rise and fall time interval when switching a resis-

tive load, V GS remains virtually constant at a level known as

the plateau voltage, V SGP . Therefore, rise and fall times may

be approximated by the following:

t r = Q 2 x R G /(V GG – V GSP )

t f = Q 2 x R G /V GSP

where

V GG = the gate drive voltage, which varies from zero to V GG

R G = the gate drive resistance

and Q 2 and V GSP are read from the gate charge curve.

During the turn–on and turn–off delay times, gate current is

not constant. The simplest calculation uses appropriate val-

ues from the capacitance curves in a standard equation for

voltage change in an RC network. The equations are:

t d(on) = R G C iss In [V GG /(V GG – V GSP )]

t d(off) = R G C iss In (V GG /V GSP )

The capacitance (C iss ) is read from the capacitance curve at

a voltage corresponding to the off–state condition when cal-

culating t d(on) and is read at a voltage corresponding to the

on–state when calculating t d(off) .

At high switching speeds, parasitic circuit elements com-

plicate the analysis. The inductance of the MOSFET source

lead, inside the package and in the circuit wiring which is

common to both the drain and gate current paths, produces a

voltage at the source which reduces the gate drive current.

The voltage is determined by Ldi/dt, but since di/dt is a func-

tion of drain current, the mathematical solution is complex.

The MOSFET output capacitance also complicates the

mathematics. And finally, MOSFETs have finite internal gate

resistance which effectively adds to the resistance of the

driving source, but the internal resistance is difficult to mea-

sure and, consequently, is not specified.

The resistive switching time variation versus gate resis-

tance (Figure 9) shows how typical switching performance is

affected by the parasitic circuit elements. If the parasitics

were not present, the slope of the curves would maintain a

value of unity regardless of the switching speed. The circuit

used to obtain the data is constructed to minimize common

inductance in the drain and gate circuit loops and is believed

readily achievable with board mounted components. Most

power electronic loads are inductive; the data in the figure is

taken with a resistive load, which approximates an optimally

snubbed inductive load. Power MOSFETs may be safely op-

erated into an inductive load; however, snubbing reduces

switching losses.

1800

V DS = 0 V V GS = 0 V

T J = 25 ° C

1600

C iss

1400

1200

1000

C rss

800

C iss

600

400

C oss

C rss

200

V GS

V DS

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Motorola TMOS Power MOSFET Transistor Device Data

1000

V DD = 30 V

I D = 12 A

V GS = 10 V

T J = 25 ° C

V GS

100

t r

t f

t d(off)

t d(on)

I D = 12 A

T J = 25 ° C

V DS

10 12

100

Q T , TOTAL CHARGE (nC)

R G , GATE RESISTANCE (OHMS)

Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

V GS = 0 V

T J = 25

0.5

0.7

0.9

1.1

1.3

1.5

1.7

1.9

V SD , SOURCE–TO–DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

C. Peak

repetitive pulsed power limits are determined by using the

thermal response data in conjunction with the procedures

discussed in AN569, “Transient Thermal Resistance–General

Data and Its Use.”

Switching between the off–state and the on–state may tra-

verse any load line provided neither rated peak current (I DM )

nor rated voltage (V DSS ) is exceeded and the transition time

(t r ,t f ) do not exceed 10 m s. In addition the total power aver-

aged over a complete switching cycle must not exceed

(T J(MAX) – T C )/(R

able operation, the stored energy from circuit inductance dis-

sipated in the transistor while in avalanche must be less than

the rated limit and adjusted for operating conditions differing

from those specified. Although industry practice is to rate in

terms of energy, avalanche energy capability is not a

constant. The energy rating decreases non–linearly with an

increase of peak current in avalanche and peak junction tem-

perature.

Although many E–FETs can withstand the stress of drain–

to–source avalanche at currents up to rated pulsed current

(I DM ), the energy rating is specified at rated continuous cur-

rent (I D ), in accordance with industry custom. The energy rat-

ing must be derated for temperature as shown in the

accompanying graph (Figure 13). Maximum energy at cur-

rents below rated continuous I D can safely be assumed to

equal the values indicated.

q JC ).

A Power MOSFET designated E–FET can be safely used

in switching circuits with unclamped inductive loads. For reli-

Motorola TMOS Power MOSFET Transistor Device Data

The Forward Biased Safe Operating Area curves define

the maximum simultaneous drain–to–source voltage and

drain current that a transistor can handle safely when it is for-

ward biased. Curves are based upon maximum peak junc-

tion temperature and a case temperature (T C ) of 25

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