Designing Embedded Processors - A Low Power Perspective.pdf

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DESIGNING EMBEDDED PROCESSORS
Designing Embedded Processors
A Low Power Perspective
Edited by
J. HENKEL
University of Karlsruhe,
Germany
and
S. PARAMESWARAN
University of South Wales,
NSW, Australia
813357819.002.png
A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN 978-1-4020-5868-4 (HB)
ISBN 978-1-4020-5869-1 (e-book)
Published by Springer,
P.O. Box 17, 3300 AA Dordrecht, The Netherlands.
www.springer.com
Printed on acid-free paper
All Rights Reserved
© 2007 Springer
No part of this work may be reproduced, stored in a retrieval system, or transmitted
in any form or by any means, electronic, mechanical, photocopying, microfilming, recording
or otherwise, without written permission from the Publisher, with the exception
of any material supplied specifically for the purpose of being entered
and executed on a computer system, for exclusive use by the purchaser of the work.
Contents
Foreword: Embedded Processors – what is next?
xv
J org Henkel and Sri Parameswaran
1.
Philosophy of This Book
xvi
2.
Contents
xvi
Part I
Application Specific Embedded Processors
1
Application-Specific Embedded Processors
3
J org Henkel, Sri Parameswaran, and Newton Cheung
1.
Introduction and Motivation
4
1.1
Some Trends in Designing SOCs
6
1.2
Extensible Processor Platforms as a Possible Solution
7
1.3
Open Issues and Key Techniques
10
1.4
SOC Design Distinction
11
2.
Challenges in Embedded Extensible Processor Design
12
2.1
Code Segment Identification
12
2.2
Extensible Instruction Generation
14
2.3
Architectural Customization Selection
17
2.4
Summary
19
References
19
2
Low-Power Design with NISC Technology
25
Bita Gorjiara, Mehrdad Reshadi, and Daniel Gajski
1.
Introduction
25
2.
Overview of NISC Technology
27
3.
NISC Compared to Other Approaches
29
3.1
NISC vs. ASIP
29
3.2
NISC vs. VLIW
30
3.3
NISC vs. Microcoded Architectures
30
3.4
NISC vs. HLS
31
4.
Overview of the Compilation Algorithm
32
5.
Power Optimizations in NISC
37
5.1
Reducing the Switching Capacitance
37
5.2
Reducing Number of Cycles
39
6.
Experiments
39
6.1
The Effect of Pipeline Structure on Power and Performance
39
6.2
Custom Datapath Design for DCT
42
v

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