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In professional electronics today, some of the greatest
advances have been made in the field of programma-
ble devices, especially those designed to implement
logic functions. From using boards full of discrete logic
devices (typically 74 series devices), now many complex
functions are often implemented in a single program-
mable device. This is achieved by the use of devices
with an ever-growing number of ‘gates’ and pins. Today,
these devices are almost always Field Programmable
Gate Arrays (FPGAs).
Atmel UK Limited
Atmel FPGA
design course (1)
part 1: introduction
So what exactly
is an FPGA? The name
suggests an array of logic gates that can
be programmed to achieve a particular
function. This is largely true, if we consider
the smallest programmable logic struc-
ture not to be a gate but an element
called a
cell
. Not only the cells are pro-
grammable, but also their interconnec-
tions, allowing more complex functions
to be built up from these comparatively
simple cells. The cells are arranged into
a symmetrical array as illustrated in
Fig-
ure 1
. There are also input/output pins on
the device that are used to connect sig-
nals into the array. Cells may be
addressed from several sides by so-
called
repeaters
(see
Figure 2
).
The Interactive FPGA Architecture
Guide included on the cover-mounted
CD-ROM is a good place to start look-
ing at the architec-
ture of Atmel’s newest FPGA
family, the AT40K. This file
allows you to navigate
through the hierarchy of an
AT40K FPGA, and examine all of its most
salient features. Whilst there is no need
to look into this right now, and indeed
FPGAs may be treated as ‘black boxes’
to some extent, it is useful to have an
appreciation of the internal workings of
such a device.
Five planes of busing structures
allow high confidence of being able to
route a design in the smallest possible
part. The structure of a busing plane is
illustrated in
Figure 3
. It also allows the
user I/Os to be ‘locked’ early in the
design cycle, whilst knowing the design
will be routable in the chosen device.
The octagonal device structure as illus-
trated in
Figure 4a
allows the direct
connection of a cell to its eight nearest
neighbours. This allows the implemen-
tation of very efficient array multipliers
and other DSP functions without the use
of a busing resource. As shown in
Fig-
ure 4b
, each cell also has a number of
connections to the bus.
There are
multiple functions avail-
able on all of the IO pins
, such as
Open Drain outputs, and Schmitt trig-
gers on the inputs. These can all be
configured on a pin by pin basis, allow-
ing each IO line to be suited to its func-
tion. There are two IOs per edge core
cell, the
Primary and Secondary IOs
.
The Primary IOs interface directly into
core cell and to the repeaters of the
adjacent busing resource. The Sec-
ondary IOs connect on the diagonal
connections of the cells above and
below it, and into the adjacent busing
resource via the nearest repeaters. In
this way, the corner pins can be used
as IOs, often a bottleneck in IO inten-
sive designs. The device’s IOs are
fully
PCI compliant
, with additional clocks
for PCI operation. This allows the imple-
FPGA key benefits
The FPGA architecture includes distrib-
uted
on-board user SRAM
, available
for the construction of single and dual
port synchronous RAMs (random-
access memories) as well as on-board
FIFOs (first-in, first-out). This allow fast, low
cost designs to be created, as no logic
cells are used as storage elements, so
forcing the design into a larger, more
expensive device.
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mentation of PCI interfaces without
additional devices.
In addition to the fast PCI compliant
clocks, we have
8 global clock sig-
nals with power conservation modes
available throughout the device.
The devices also exhibit
very low
power consumption
of less than
200 µA in standby mode, and around
2 mA/MHz in operation.
All of the above features combined
with an advanced set of design tools
place the AT40K in a position to offer a
great deal to the FPGA designer and
user.
Curriculum
Although the FPGA could seem the
answer to every designer’s dream,
three aspects of FPGA usage have
made their use by hobbyists unfeasible.
These are:
1.
the design methodology;
2.
software development tools;
3.
hardware development tools.
In this, the first of three instalments to be
published over the next few monhts, we
will look at the first aspect, and discover
the ways in which we can describe the
hardware we want to implement. In
subsequent months we will cover the
use of the design and hardware tools,
presented free with this month’s maga-
zine, leading up to the use of the Atmel
AT40K hardware development environ-
ment.
To alleviate the cost issues con-
cerned when using an FPGA, Atmel
have provided their suite of design tools
for FPGAs on the CD-ROM mounted on
the cover of this magazine. This disk
includes fully working versions of the
Atmel Place and Route software, a
VHDL synthesis tool and a VHDL tem-
plate generator, all free of charge.
Figure 1. Symmetrical array surrounded by I/O (AT40K20).
their connectivity is totally unambigu-
ous. However, the exact logical imple-
mentation of a function required within
an FPGA is often not required. Within a
schematic it may be necessary to cre-
ate many sheets to implement a
counter, which, as we will see, can be
implemented in a much more efficient
way, which gives the same results, with
much less scope for error.
Schematic capture for FPGA design
still remains popular though, through the
use of utilities that allow the building of
high level functional blocks, or macros.
These macros are used as complete
components, and so the design with
schematics becomes easier. The final
disadvantage with schematic capture is
that the third party tool sets are expen-
sive, and often require a very high level
of computing power just to run them.
Often, FPGA manufacturers have ‘free’
versions for their tools, but usually the
average hobbyist is not in a position to
receive such a package. Simulation
packages add to this cost, and with all
the potential margins for error within
schematic capture, simulation becomes
a vital part of the design flow.
Just away from schematic capture,
but again in the high cost realm are the
graphical state machine entry pack-
ages
. These are usually a bolt on to a
schematic capture to allow the design
of complex state machines to become
easier. To describe a state machine in
logic gates is a time consuming busi-
ness. Firstly the state machine has to be
designed, then the logic equations
worked out and minimised, and finally
equations need to be implemented in
the schematic. These packages allow
the user to draw his state machine in
the usual form of states represented by
a circle, with conditional connections
between the states. The state diagram
is then translated into Boolean equa-
tions for the FPGA design routines.
The third popular method for the
design of FPGAs is by
text entry meth-
ods
. There are several Hardware
Description Languages (HDLs) available,
all of which allow the specification of a
function to be described, be it as a list
of reduced Boolean equations, or as a
functional description of the design. The
HDL that has become industry standard
is called VHDL (VHSIC Hardware Descrip-
tion Language). An offshoot of the Very
High Speed Integrated Circuit (VHSIC)
program run by the United States
Department of Defence in the 1970s,
VHDL allows the description of a circuit
from hardware independent level down
to the individual gate level. Whilst this
series of articles is by no means
designed to teach you VHDL, we will
touch on several aspects of VHDL
design through the use of the Atmel 40K
tools supplied on the free CD-ROM.
FPGA design methods
Design methods are the means in
which we capture the design to be
implemented in the FPGA. There are
several ways in which this can be
achieved. Firstly, and traditionally the
most popular is
schematic capture
.
The traditional design method for all
electronics is by using a picture to
describe the functionality and con-
nectivity in a design. A circuit is
described at component level, and
within a digital design, this usually
means low level logic gates (typically).
This is absolutely vital in the design of a
PCB (printed circuit board), so that the
correct functionality of devices and
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So VHDL it is, then
The reason for this emphasis on VHDL is
that the tools supplied on the cover-
mounted CD-ROM include a VHDL syn-
thesis environment. This is used for the
example we will look at in the next arti-
cle, and for you to use for your own
projects.
So what does VHDL give us that other
design methods do not? Firstly, at a
high level, it gives us hardware-inde-
pendent design. This means that in the-
ory we can write our VHDL, and then
implement in any manufacturer’s
device. Whilst in theory correct, to get
the best out of a given architecture, dif-
ferent coding styles may be required
(just as in writing software).
Secondly, control over large designs
is more powerful. A schematic design
can range over several sheets, all of
which have cross connections. As most
schematics are ‘flat’, i.e., with no hier-
archy within them, it can be easy to
lose control of the design. VHDL may
be (and usually is) written in small mod-
ules which can be used in higher level
blocks and in multiple designs. This
modularity makes the building of
libraries of ‘components’ which are suit-
able for re-use a reality. We shall see
how re-use integrates into the FPGA
software development tools in the next
instalment.
Thirdly, a lot of work in calculating
the Boolean algebra required to imple-
ment higher level functions is removed.
To draw the function of an 8-bit equal-
ity comparator in discrete logic would
require, for example, 8
Figure 2. Floorplan (representative portion)
And if the function was ‘greater than or
equal to’? Again a simple change to
the VHDL:
eq := 0;
END IF;
IF (a>=b) THEN
eq := 1;
So we can quickly see, without having
a great appreciation of VHDL that a
high level function, typical of those
required in an FPGA design, is very eas-
ELSE
×
×
2 input AND
8 input AND gate (there
are other ways of implementing this of
course). There would also be 25 inter-
connects. To achieve this in VHDL would
take the following construct:
IF (a=b) THEN
eq := 1;
ELSE
eq := 0;
END IF;
8 inputs and
EQ is the output. This does not look like
a great saving in effort. Consider,
though, if the required function
changed to the output was a logical ‘1’
if
a
was greater than
b
. This becomes a
very messy schematic, but in VHDL we
can simply change one line, i.e.,
×
IF (a>b) THEN
eq := 1;
ELSE
eq := 0;
END IF;
Figure 3. Busing plane (one of five).
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gates and 1
Where
a
and
b
are the 2
ily created and maintained using VHDL.
Simulation is supported through VHDL
by files called
testbenches
. These are
only appropriate for gate (or cell) level
designs known as
Register Transfer
Level (RTL) designs
. Simulation requires
two aspects: the description of the
design
and the
stimulus
file. However,
as the VHDL designs we are looking at
are very simple, there are very few cir-
cumstances where we would actually
require simulation. The cover CD-ROM
does not include a VHDL simulation
package, although there are several
available on the Internet.
We have now seen that VHDL can
offer whatever schematic capture can
offer us and more, and it is from this
point of view that we will work on our
designs in VHDL.
a
b
Figure 4. (a) Cell-to-cell connections; (b) cell-to-bus connections.
Next time
In the next instalment we will look at
how we can take a VHDL file, synthesise
it and use the resulting file to place and
route an FPGA.
After VHDL
This process is called
synthesis
. The
CD-ROM comes complete with a syn-
thesis tool which we can use to gener-
ate the appropriate file for our place
and route routines.
Once we have written our VHDL, we
need to translate this into a form under-
standable by our FPGA design tools.
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