power on sequence introduction.pdf
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
Power On Sequence
Sephiroth Kwon
GRMA
GRMA
26-05-2009
OUTLINE
•
General Power On Sequence
•
Power On Sequence (P5Q3)
Power On Sequence (P5Q3)
•
•
Power On Sequence (M3N78-VM)
•
No Power Problem Debug Point
No Power Problem Debug Point
•
General Power On Sequence
PSON#
ATX
TOP VIEW
PANNEL
PWRBTN
+ 5
+ 12
Cap./
Res.
3VSB
5VSB to 3VSB
Linear Reg.
+ 5
5VSB
1/0
-5
PWOK
5VSB
1
1
GND
GND
GND
GND
1
GND
+ 5
GND
GND
0
+ 5
PSON
GND
GND
IT8282
- 12V
+ 3V
+ 3V
+ 3V
Super I/O
PSON Pull low circuit
PSON
PWRBTN
0
South
Bridge
General Power On Sequence
+ 5
+ 12
CPU SOCKET
+ 5
5VSB
-5
PWOK
(2)
CPURST
(5)
GND
GND
PG1
GND
+ 5
IDERST
S
GND
GND
Circuit
IDE SLOT
(4)
+ 5
PWROK
PSON
PCIRST
(3)
GND
GND
PCI SLOT
North Bridge
North Bridge
- 12V
12V
+3V
+ 3V
+ 3V
+ 3V
Circuit
PSON
South Bridge
(1)
PANNEL
PWRBTN
Power On Sequence (P5Q3 Sample)
S_PLTRST
S_PLTRST
GMCH
POWER
BATXPWROK
B_ATX_PWROK
10
POWER
SUPPLY
USER PRESS
CRTL+ATL+DEL
O_PWROK
O_PWROK_NB
7
O_PSON#
6
7
9
O_PCIRST#_PCIEX16_12
PCI_PCIEX16
Super I/O
O_PCIRST#_PCIEX1_123
3
USER PRESS
POWER BTN
PCI_PCIEX1
9
2
5
5
4
7
O_PWRBTNIN#
O PCIRST# SLOT
O_PCIRST#_SLOT
PCI SLOT
P_VRM_GD
EPU
7
3
4
User
press
Rest
button
RSTCON#
RSTCON#
S_PCIRST#
8
TPM
ICH10R
JMB363
S_TRCRST#
User clear
User clear
CMOS
VA6308P
1
8
8
S_PLTRST#
CPU
H CPUPWRGD
H_CPUPWRGD
CPU
LAN
Plik z chomika:
mfireb
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