barc_final.pdf

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VHDL Front-end
VHDL Front end
53597748.002.png
Entity, Architecture and Process
a
entity mux is
port( a, b, c, d : in bit;
s0, s1: in bit;
x: out bit);
end mux;
b
Mux
c
x
d
s0 s1
architecture arch_mux of mux is else sel<="11";
begin end if;
process (a, b, c, d, s0, s1) case sel is
variable sel: std_logic_vector(1 downto 0); when "00" => x<= a;
begin
when "10" => x<= c;
if s0='0' and s1= '0' then
when "01" => x<= b;
if s0='0' and s1= '0' then
when "01" => x<= b;
sel<="00";
when others => x<= d;
sel<="00";
when others => x<= d;
elsif s0='1' and s1= '0' then
end case;
elsif s0='1' and s1= '0' then
end case;
sel<="01";
end process;
sel<="01";
end process;
elsif s0='0' and s1= '1' then
end arch_mux;
elsif s0='0' and s1= '1' then
end arch_mux;
sel<="10";
sel<="10";
architecture arch_mux of mux is else sel<="11";
begin end if;
process (a, b, c, d, s0, s1) case sel is
variable sel: std_logic_vector(1 downto 0); when "00" => x<= a;
begin
when "10" => x<= c;
53597748.003.png
Behavioral & Structural coding
styles
architecture structural_mux of mux is
begin
U1: inverter port map (in1 =>s0,
x=>s0_inv);
signal s0_inv, s1_inv, x1, x2, x3, x4 : bit;
U2: inverter (in1=>s1, x=>s1_inv);
U3: andgate (a=>a, b=>s0_inv,
c=>s1_inv, d=>x1);
signal s0_inv, s1_inv, x1, x2, x3, x4 : bit;
U2: inverter (in1=>s1, x=>s1_inv);
U3: andgate (a=>a, b=>s0_inv,
c=>s1_inv, d=>x1);
component andgate
U4: andgate (a=>b, b=>s0, c=>s1_inv,
component andgate
U4: andgate (a=>b, b=>s0, c=>s1_inv,
port ( a, b, c: in bit; d: out bit);
d=>x2);
end component; U5: andgate (a=>c, b=>s0_inv, c=>s1,
d=>x3);
component inverter U6: andgate (a=>d, b=>s0, c=>s1,
port ( in1: in bit; x: out bit);
port ( a, b, c: in bit; d: out bit);
d=>x2);
end component; U5: andgate (a=>c, b=>s0_inv, c=>s1,
d=>x3);
component inverter U6: andgate (a=>d, b=>s0, c=>s1,
port ( in1: in bit; x: out bit);
d=>x4);
d=>x4);
end component;
U7: orgate (a=>a, b=>b, c=>c, d=>d,
x=>x);
end component;
U7: orgate (a=>a, b=>b, c=>c, d=>d,
x=>x);
component orgate
end structural_mux;
component orgate
end structural_mux;
port ( a, b, c, d : in bit; x: out bit);
end component;
port ( a, b, c, d : in bit; x: out bit);
end component;
architecture structural_mux of mux is
begin
U1: inverter port map (in1 =>s0,
x=>s0_inv);
53597748.004.png
Event-driven Simulation
• Event: occurrence of a signal change (transaction)
• When an event occurs, need to handle it
(execution)
– execute any concurrent statements that are
sensitive to the change
– activate a waiting process if the condition
becomes true
• The execution triggered by an event may generate
future events
– sig_a <= a_in after 5 ns;
53597748.005.png
Event-driven Simulation
Initialization
No future event
find the next event(s)
exit
execute statements
activated by the event(s)
generate future events
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