W39V040FA.pdf

W39V040FA

512K × 8 CMOS FLASH MEMORY

WITH FWH INTERFACE

1. GENERAL DESCRIPTION

The W39V040FA is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K × 8 bits. For

flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes, which are

composed of 16 smaller even pages with 4 Kbytes. The device can be programmed and erased in-

system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture

of the W39V040FA results in fast program/erase operations with extremely low current consumption.

This device can operate at two modes, Programmer bus interface mode and FWH bus interface

mode. As in the Programmer interface mode, it acts like the traditional flash but with a multiplexed

address inputs. But in the FWH interface mode, this device complies with the Intel FWH specification.

The device can also be programmed and erased using standard EPROM programmers.

2. FEATURES

• Single 3.3-volt operations:

− 3.3-volt read

− 3.3-volt erase

− 3.3-volt program

• Fast Program operation:

− Byte-by-Byte programming: 35 µ S (typ.)

• Fast erase operation:

− Chip erase 100 mS (max.)

− Sector erase 25 mS (max.)

− Page erase 25 mS (max.)

• Fast Read access time: Tkq 11 nS

• Endurance: 10K cycles (typ.)

• Twenty-year data retention

• 8 Even sectors with 64K bytes each, which is

composed of 16 flexible pages with 4K bytes

• Any individual sector or page can be erased

• Hardware protection:

− Optional 16K byte or 64K byte Top Boot

Block with lockout protection

− #TBL & #WP support the whole chip

hardware protection

• Flexible 4K-page size can be used as

Parameter Blocks

• Low power consumption

− Active current: 12.5 mA (typ. for FWH mode)

• Automatic program and erase timing with

internalV PP generation

• End of program or erase detection

− Toggle bit

− Data polling

• Latched address and data

• TTL compatible I/O

• Available packages: 32L PLCC, 32L STSOP,

40L TSOP (10 x 20 mm)

Publication Release Date: December 19, 2002

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Revision A2

W39V040FA

3. PIN CONFIGURATIONS

4. BLOCK DIAGRAM

#WP

#TBL

7FFFF

BOOT BLOCK 64K BYTES

Optional

16KBytes

Boot Block

FWH

Interface

CLK

FWH4

MAIN MEMORY BLOCK6

64K BYTES

70000

6FFFF

60000

5FFFF

7C000

7BFFF

4K Page

MAIN MEMORY BLOCK5

64K BYTES

MAIN MEMORY BLOCK4

64K BYTES

MAIN MEMORY BLOCK3

64K BYTES

4K Page

#INIT

50000

4FFFF

#RESET

4K Page

40000

3FFFF

4K Page

A7(FGPI1)

A6(FGPI0)

R/#C

V SS

30000

2FFFF

4K Page

A[10:0]

DQ[7:0]

#OE

#WE

MAIN MEMORY BLOCK2

64K BYTES

A5(#WP)

Program-

mer

Interface

20000

1FFFF

10000

0FFFF

A4(#TBL)

A3(ID3)

A2(ID2)

A1(ID1)

A0(ID0)

4K Page

32L PLCC

V DD

MAIN MEMORY BLOCK1

64K BYTES

#OE(#INIT)

#WE(FWH4)

MAIN MEMORY BLOCK0

64K BYTES

4K Page

00000

70000

DQ0(FWH0)

DQ7(RSV)

5. PIN DESCRIPTION

INTERFACE

SYM.

PIN NAME

PGM FWH

1 14

3 31

2 27

#WE(FWH4)

Interface Mode Selection

VDD

V SS

DQ7(RSV)

DQ6(RSV)

#RESET

Reset

R/#C(CLK)

A10(FGPI4)

DQ5(RSV)

DQ4(RSV)

DQ3(FWH3)

#INIT

Initialize

V DD

32L STSOP

A9(FGPI3)

A8(FGPI2)

V SS

#TBL

#RESET

DQ2(FWH2)

DQ1(FWH1)

DQ0(FWH0)

Top Boot Block Lock

#WP

A7(FGPI1)

A6(FGPI0)

1 17

A0(ID0)

Write Protect

A1(ID1)

A5(#WP)

A4(#TBL)

A2(ID2)

A3(ID3)

CLK

CLK Input

FGPI[4:0]

General Purpose Inputs

VSS

ID[3:0]

Identification Inputs They

Are Internal Pull Down to

Vss

VDD

#WE(FWH4)

#OE(#INIT)

FWH[3:0]

Address/Data Inputs

DQ7(RSV)

DQ6(RSV)

A10(FGPI4)

FWH4

FWH Cycle Initial

DQ5(RSV)

DQ4(RSV)

CLK

R/#C

Row/Column Select

VDD

40L TSOP

VDD

VSS

A[10:0]

Address Inputs

#RESET

VSS

DQ3(FWH3)

DQ2(FWH2)

DQ1(FWH1)

DQ0(FWH0)

DQ[7:0]

Data Inputs/Outputs

A9(FGPI3)

A8(FGPI2)

#OE

Output Enable

A7(FGPI1)

A6(FGPI0)

A0(ID0)

A1(ID1)

A2(ID2)

A3(ID3)

#WE

Write Enable

A5(#WP)

A4(#TBL)

V DD

Power Supply

V SS

Ground

RSV

Reserved Pins

No Connection

- 2 -

FWH[3:0]

#OE(#INIT)

W39V040FA

6. FUNCTIONAL DESCRIPTION

Interface Mode Selection and Description

This device can operate in two interface modes, one is Programmer interface mode, and the other is

FWH interface mode. The IC pin of the device provides the control between these two interface

modes. These interface modes need to be configured before power up or return from #RESET . When

IC pin is set to high state, the device will be in the Programmer mode; while the IC pin is set to low

state (or leaved no connection), it will be in the FWH mode. In Programmer mode, this device just

behaves like traditional flash parts with 8 data lines. But the row and column address inputs are

multiplexed. The row address are mapped to the higher internal address A[18:11]. And the column

address are mapped to the lower internal address A[10:0]. For FWH mode, it complies with the FWH

Interface Specification. Through the FWH[3:0] and FWH4 to communicate with the system chipset .

Read (Write) Mode

In Programmer interface mode, the read (write) operation of the W39V040FA is controlled by #OE

(#WE). The #OE (#WE) is held low for the host to obtain (write) data from (to) the outputs (inputs).

#OE is the output control and is used to gate data from the output pins. The data bus is in high

impedance state when #OE is high. As for in the FWH interface mode, the read or write is determined

by the "bit 0 & bit 1 of START CYCLE ". Refer to the FWH cycle definition and timing waveforms for

further details.

Reset Operation

The #RESET input pin can be used in some application. When #RESET pin is at high state, the

device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all

outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device

will return to read or standby mode, it depends on the control signals.

Boot Block Operation and Hardware Protection at Initial- #TBL & #WP

There are two alternatives to set the boot block. Either 16K-byte or 64K-byte in the top location of this

device can be locked as boot block, which can be used to store boot codes. It is located in the last

16K/64K bytes of the memory with the address range from 7C000(hex)/70000(hex) to 7FFFF(hex).

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the

data for the designated block cannot be erased or programmed (programming lockout), other memory

locations can be changed by the regular programming method.

Besides the software method, there is a hardware method to protect the top boot block and other

sectors. Before power on programmer, tie the #TBL pin to low state and then the top boot block will

not be programmed/erased. If #WP pin is tied to low state before power on, the other sectors will not

be programmed/erased.

In order to detect whether the boot block feature is set on or not, users can perform software

command sequence: enter the product identification mode (see Command Codes for

Identification/Boot Block Lockout Detection for specific code), and then read from address

7FFF2(hex). If the DQ0/DQ1 output data is "1," the 64Kbytes/16Kbytes boot block programming

lockout feature will be activated; if the DQ0/DQ1 output data is "0," the lockout feature will be

inactivated and the boot block can be erased/programmed. But the hardware protection will override

the software lock setting, i.e., while the #TBL pin is trapped at low state, the top boot block cannot be

Publication Release Date: December 19, 2002

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Revision A2

W39V040FA

programmed/erased whether the output data, DQ0/DQ1 at the address 7FFF2, is "0" or "1". The #TBL

will lock the whole 64Kbytes top boot block, it will not partially lock the 16Kbytes boot block. You can

check the DQ2/DQ3 at the address 7FFF2 to see whether the #TBL/#WP pin is in low or high state. If

the DQ2 is "0", it means the #TBL pin is tied to high state. In such condition, whether boot block can

be programmed/erased or not will depend on software setting. On the other hand, if the DQ2 is "1", it

means the #TBL pin is tied to low state, then boot block is locked no matter how the software is set.

Like the DQ2, the DQ3 inversely mirrors the #WP state. If the DQ3 is "0", it means the #WP pin is in

high state, then all the sectors except the boot block can be programmed/erased. On the other hand, if

the DQ3 is "1", then all the sectors except the boot block are programmed/erased inhibited.

To return to normal operation, perform a three-byte command sequence (or an alternate single-byte

command) to exit the identification mode. For the specific code, see Command Codes for

Identification/Boot Block Lockout Detection.

Chip Erase Operation

The chip-erase mode can be initiated by a six-byte command sequence. After the command loading

cycle, the device enters the internal chip erase mode, which is automatically timed and will be

completed within fast 100 mS (max). The host system is not required to provide any control or timing

during this operation. If the boot block programming lockout is activated, only the data in the other

memory sectors will be erased to FF(hex) while the data in the boot block will not be erased (remains

as the same state before the chip erase operation). The entire memory array will be erased to FF(hex)

by the chip erase operation if the boot block programming lockout feature is not activated. The device

will automatically return to normal read mode after the erase operation completed. Data polling and/or

Toggle Bits can be used to detect end of erase cycle.

Sector/Page Erase Command

Sector/page erase is a six bus cycles operation. There are two "unlock" write cycles, followed by

writing the "set-up" command. Two more "unlock" write cycles then follows by the sector/page erase

command. The sector/page address (any address location within the desired sector/page) is latched

on the falling edge of #WE, while the command (30H/50H) is latched on the rising edge of #WE.

Sector/page erase does not require the user to program the device prior to erase. When erasing a

sector/page or sectors/pages the remaining unselected sectors/pages are not affected. The system is

not required to provide any controls or timings during these operations.

The automatic sector/page erase begins after the erase command is completed, right from the rising

edge of the #WE pulse for the last sector/page erase command pulse and terminates when the data

on DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be

performed at an address within any of the sectors/pages being erased.

Refer to the Erase Command flow Chart using typical command strings and bus operations.

Program Operation

The W39V040FA is programmed on a byte-by-byte basis. Program operation can only change logical

data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or

boot block from "0" to "1", is needed before programming.

The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte

Programming). The device will internally enter the program operation immediately after the byte-

program command is entered. The internal program timer will automatically time-out (50 µ S max. -

T BP ) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be

used to detect end of program cycle.

- 4 -

W39V040FA

Hardware Data Protection

The integrity of the data stored in the W39V040FA is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) V DD Power Up/Down Detection: The programming and read operation are inhibited when V DD is

less than 1.5V typical.

(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents

inadvertent writes during power-up or power-down periods.

(4) V DD power-on delay: When V DD has reached its sense level, the device will automatically time-out

5 mS before any write (erase/program) operation.

Data Polling (DQ 7 )- Write Status Detection

The W39V040FA includes a data polling feature to indicate the end of a program or erase cycle.

When the W39V040FA is in the internal program or erase cycle, any attempts to read DQ 7 of the last

byte loaded will receive the complement of the true data. Once the program or erase cycle is

completed, DQ 7 will show the true data. Note that DQ 7 will show logical "0" during the erase cycle,

and when erase cycle has been completed it becomes logical "1" or true data.

Toggle Bit (DQ 6 )- Write Status Detection

In addition to data polling, the W39V040FA provides another method for determining the end of a

program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ 6 will

produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between

0's and 1's will stop. The device is then ready for the next operation.

There are three kinds of registers on this device, the General Purpose Input Registers, the Block Lock

Control Registers and Product Identification Registers. Users can access these registers through

respective address in the 4Gbytes memory map. There are detail descriptions in the sections below.

General Purpose Inputs Register

This register reads the FGPI[4:0] pins on the W39V040FA.This is a pass-through register which can

read via memory address FFBC0100(hex). Since it is pass-through register, there is no default value.

G PI Register Ta ble

BIT

FUNCTION

7 − 5

Reserved

Read FGPI4 pin status

Read FGPI3 pin status

Read FGPI2 pin status

Read FGPI1 pin status

Read FGPI0 pin status

Publication Release Date: December 19, 2002

- 5 -

Revision A2

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