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A
PPLICATION
N
OTE
A V A I L A B L E
3 or 4 Cell Li-Ion BATTERY PACKS
Preliminary Information
X3100
3 or 4 Cell Li-Ion Battery Protection and Monitor IC
FEATURE
• Software selectable safety levels and variable
protect detection/release times
• Integrated FET Drive Circuitry
• Cell voltage and current monitoring
• 0.5% accurate voltage regulator
• Integrated 4kbit EEPROM
BENEFIT
• Optimize protection for chosen cells to allow
maximum use of pack capacity.
• Reduce component count and cost
• Simplify implementation of fuel gauge
• Accurate voltage and current measurements
• Record battery history to optimize fuel gauge,
track pack failures and monitor system use
• Reduce power to extend battery life
• Increase battery capacity and improve cycle life
battery life
• Flexible Power Management with 1µA Sleep mode
• Cell balancing control
DESCRIPTION
Using an internal analog multiplexer, the X3100 also
allows battery parameters such as cell voltage and
current (using a sense resistor) to be monitored exter-
nally. An off-board microcontroller and A/D converter
can be used to implement fuel gauge and cell balanc-
ing functionality in software.
The X3100 is a protection and monitor IC for use in
battery packs consisting of 3 or 4 Lithium-Ion battery
cells. The device provides internal over-voltage,
under-voltage, and over-current protection circuitry,
internal EEPROM memory, an internal voltage regula-
tor, and internal drive circuitry for switching external
FET devices used to control cell charge, discharge,
and cell voltage balancing.
The X3100 contains a current sense amplifier. With
selectable gains of 10, 25, 80 and 160, this circuit
helps an external 10 bit A/D converter achieve better
resolution than a more expensive 14 bit converter.
Over-voltage, under-voltage, and over-current thresh-
olds can be selected independently via software and
stored in an internal non-volatile memory register.
Detection and time-out delays can also be individually
varied. Changes are made to the device via a 3MHz
SPI serial interface.
An internal 4kbit EEPROM memory featuring
IDLock
™
, allows the designer to partition and “lock in”
written battery cell/pack data.
The X3100 is housed in a 28 Pin SSOP and 28 Pin
TSSOP package.
FUNCTIONAL DIAGRAM
Vcc
RGP
RGC RGO
UVP/OCP
OVP/LMON
AS0
AS1
AS2
FET Control
Circuitry
VCELL1
CB1
5VDC
Regulator
Analog
MUX
Over-voltage
Under-voltage
Protection
&
Voltage
Sense
AO
VCELL2
Protection
Sample Rate
Timer
Internal Voltage Regulator
Power On reset &
Status Register
CB2
S0
VCELL3
4 kbit
EEPROM
CB3
SPI
I/F
SCK
Protection Circuit
Timing Control
& Configuration
Over-current
Protection &
Current Sense
Configuration
Register
Control
Register
VCELL4
CS
CB4
SI
VCS1
VCS2
OVT
UVT
OCT
Vss
Ó
Xicor, Inc. 1994, 1995, 1996, 1997, 1998, 1999, 2000 Patents Pending
9900-3012 11/1/99 CM
Characteristics subject to change without notice
1
D
6
D
7
D
1
D
2
Charge FET
P+
I
LMON
Q
2
Q
1
R
PU
Discharge FET
D
3
I
LMT
V
RGO
Q
3
3 or 4
Li-Ion cells
†
.
R
LMT
UVP/
R
T
’
OVP/LMON
uC,
ASIC
OCP
V
T
B+
RGO
RGC
Vcc
RGP
R
T
Vcc
VCELL1
R
LPF
R
CB
C
LPF
A/D Input
A/D Input
Q6
CB1
AO
A/D Reference
VCELL2
R
LPF
Input
R
CB
C
LPF
AS0
AS1
AS2
Q7
CB2
X3100
HOST
VCELL3
R
LPF
DATA
R
CB
I/F
C
LPF
Q8
CB3
VCELL4
GP
I/O
S0
R
LPF
R
CB
C
LPF
SCL
Q9
CB4
CS
SI
Vss
VCS1
VCS2
OVT
UVT
OCT
†
In the case that
3 cells are used Pin 7 MUST
be tied to Pin 9 (Vss).
P-
C
UV
C
OC
C
OV
B-
R
SENSE
X3100
Preliminary
PRINCIPLES OF OPERATION
will be ON when UVP/OCP or OVP/LMON are at level
Vss, and OFF when UVP/OCP or OVP/LMON are at
level Vcc.
The X3100 provides two distinct levels of functionality
and battery cell protection:
These pins are switched ON/OFF under certain condi-
tions in order to protect the battery cells from the dam-
age which may occur in Over-voltage, Under-voltage,
or Over-current states.
First, the device periodically monitors for over-voltage
and under-voltage protection modes, while continuously
monitoring for an over-current condition. A protection
mode violation results from an over-voltage, under-
voltage, or over-current state. The thresholds for these
states are selected by the user through software.
X3100 SPI SERIAL COMMUNICATION
The X3100 is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular micro
con
troller families. This interface u
ses
four signals, CS, SCK, SI and SO. The signal CS
when low, enables communications with the device.
The SI pin carries the input signal and SO provides the
output signal. SCK clocks data in or out. The X3100
operates in SPI mode 0 which requires SCK to be nor-
mally low when not transferring data. It also specifies
that the rising edge of SCK clocks data into the device,
while the falling edge of SCK clocks data out.
Second, a microcontroller with A/D converter can mea-
sure battery cell voltages and current via pin AO and
the on-board MUX of the X3100. The user can thus
implement protection, charge/discharge, or fuel gauge
software algorithms to suit the specific application and
characteristics of the cells used. While monitoring
these voltages, all protection circuits are monitored
continuously.
All descriptions of the operation of the X3100 contained
within this data sheet, are made with reference to the
Typical Application Circuit shown in Figure 1.
This SPI port is used to set the various internal regis-
ters, write to the EEPROM array, and select various
device functions.
The X3100 contains internal circuitry which enables
the direct drive of MOSFET devices for power switch-
ing. As shown in Figure 1, pins UVP and OVP switch
p-channel MOSFET’s (Q
The X3100 contains an 8-bit instruction regi
ster
. It is
accessed by clocking data into the SI input. CS must
be LOW during the entire operation. Table 1 contains
a list of the instructions and their opcodes. All instruc-
tions, addresses and data are transferred MSB first.
) which control cell
discharge and charge respectively. These devices shall
be referred to as the “Discharge FET” and the “Charge
FET”. Since these FETs are p-channel devices, they
and Q
1
2
Table 1. X3100 Instruction Set
Instruction
Name
Instruction
Format*
Description
WREN
0000 0110
Set the Write Enable Latch (Write Enable Operation) - Figure 16
WRDI
0000 0100
Reset the Write Enable Latch (Write Disable Operation) - Figure 16
EEWRITE
0000 0010
Write operation followed by address and data (For 4kbit EEPROM) - Figures 20,21
EEREAD
0000 0011
Read operation followed by address (For 4kbit EEPROM) - Figure 18
Write to Configuration Register (Followed by two bytes of data - Figures 3,13). Data
stored in SRAM only and will power-up to previous settings (Figures 2,4)
WCFIG
0000 1001
WCNTR
0000 1010
Write to Control Register (Followed by two bytes of data) - Figure 3
RDSTAT
0000 1011
Read contents of Status Register - Figure 15
SET IDL
0000 0001
Set EEPROM ID Lock Partition (Followed by Partition Byte) - Figure 17
EEREAD STAT
0000 0101
Reads IDLock settings & status of EEPROM EEWRITE Instruction - Figure 19
*Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
3
X3100
Preliminary
Table 2. Configuration Register Functionality
Bit(s)
Name
Function
0-5
-
(Don’t Care)
6
SWCEN
Switch cell Charge Enable threshold function ON/OFF
7
CELLN
Set the Number of Li-Ion battery Cells used (3 or 4)
8-9
VCE1-VCE0
Select Cell Charge threshold Voltage
10-11
VOC1-VOC0
Select Over-current threshold Voltage
12-13
VUV1-VUV0
Select Under-voltage threshold Voltage
14-15
VOV1-VOV0
Select Over-voltage threshold Voltage
Data
inp
ut is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then start it again to resume opera-
tions where left off.
POWER UP
DATA RECALLED
FROM SHADOW EEPROM
TO SRAM
CONFIGURATION REGISTER
CONFIGURATION REGISTER
(SRAM=OLD VALUE)
The X3100 can be configured for specific user require-
ments using the Configuration Register.
WCFIG (NEW VALUE)
The Configuration Register is realized as two bytes of
NOVRAM memory. This memory features a high-
speed static RAM (SRAM) overlaid bit-for-bit with non-
volatile “Shadow” EEPROM. An automatic array recall
operation reloads the contents of the shadow
EEPROM into the SRAM Configuration Register upon
power-up (Figure 2).
CONFIGURATION REGISTER
(SRAM=NEW VALUE)
STORE
(NEW VALUE) IN
SHADOW
EEPROM
NO
YES
POWER DOWN
POWER UP
WRITE
ENABLE
Configuration Register (SRAM)
Upper Byte
Lower Byte
WREN
DATA RECALLED
FROM SHADOW EEPROM
TO SRAM
WRITE TO
4kbit EEPROM
RECALL
RECALL
Shadow EEPROM
CONFIGURATION
REGISTER
(SRAM=OLD VALUE)
EEWRITE
POWER DOWN
POWER UP
Figure 2. Power up of
Configuration Register.
DATA RECALLED
FROM SHADOW EEPROM
TO SRAM
The Configuration Register is designed for unlimited
write operations to SRAM, and a minimum of
1,000,000 store operations to the EEPROM. Data
retention is specified to be greater than 100 years.
CONFIGURATION
REGISTER
(SRAM=NEW VALUE)
The Configuration Register consists of two bytes
(upper and lower) of data (Tables 4, 5)
.
Figure 3.
Writing to Configuration Register.
4
X3100
Preliminary
Table 3. Control Register Functionality
Bit(s)
Name
Function
0-4
-
(Don’t Care)
5-6
0, 0
Reserved—write 0 to these locations.
7
SLP
Select X3100 Sleep mode.
8-9
CSG1-CSG0
Select current sense voltage gain
10
OVPC
OVP Control: Switch pin OVP = Vcc/Vss
11
UVPC
UVP Control: Switch pin UVP = Vcc/Vss
12
CBC1
CB1 Control: Switch pin CB1 = Vcc/Vss
13
CBC2
CB2 Control: Switch pin CB2 = Vcc/Vss
14
CBC3
CB3 Control: Switch pin CB3 = Vcc/Vss
15
CBC4
CB4 Control: Switch pin CB4 = Vcc/Vss
Table 4. Configuration Register—Upper Byte
The default settings of the Configuration Register (at
shipping) are 37h and C0h for the upper and lower
bytes respectively.
15
14
13
12
11
10
9
8
VOV1
VOV0
VUV1
VUV0
VOC1
VOC0
VCE1
VCE0
CONTROL REGISTER
Table 5. Configuration Register—Lower Byte
The Control Register is realized as two bytes of vola-
tile RAM (Table 6, 7). This register can be written to by
first issuing the WCNTR Instruction on SI, followed by
two bytes of the Control Register data (Figure 15).
7
6
5
4
3
2
1
0
CELLN
SWCEN
x
x
x
x
x
x
The Configuration Register can be written, by first writ-
ing the WCFIG Instruction on the SI pin, followed by
two bytes of data (Figure 14). The quantities that can
be set in the Configuration Register are listed in Table 2.
Table 6. Control Register—Upper Byte
15
14
13
12
11
10
9
8
CBC4
CBC3
CBC2
CBC1
UVPC
OVPC
CSG1
CSG0
It should be noted that the bits of the shadow
EEPROM are for the dedicated use of the Configura-
tion Register, and are NOT part of the general purpose
4kbit EEPROM array.
Table 7. Control Register—Lower Byte
7
6
5
4
3
2
1
0
SLP
0
0
x
x
x
x
x
After writing to this register using a WCFIG Instruction,
data will be stored only in the SRAM of the Configura-
tion Register. In order to store data in shadow
EEPROM, a WREN Instruction (Figure 17), followed
by a EEWRITE to any address of the 4kbit EEPROM
memory array must occur (Figure 21). This sequence
initiates an internal nonvolatile write cycle which per-
mits data to be stored in the shadow EEPROM cells. It
must be noted that even though a EEWRITE is made
to the general purpose 4kbit EEPROM array, the value
and address to which it is written, is unimportant. If this
procedure is not followed, the Configuration Register
will power up to the last previously stored values fol-
lowing a power down sequence (Figure 3).
Since the Control Register is realized in Volatile mem-
ory, data will be lost following a power down and
power up sequence. The default value of the Control
Register on initial power up or when exiting the SLEEP
MODE is 00h (for both upper and lower bytes respec-
tively). The functions that can be manipulated by the
Control Register are shown in Table 3.
5
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