74HC192.PDF

M54/M74HC192

M54/M74HC193

HC192 - SYNCHRONOUS UP/DOWN DECADE COUNTER

HC193 - SYNCHRONOUS UP/DOWN BINARY COUNTER

. HIGH SPEED

f MAX = 54 MHz (TYP.) AT V CC =5V

. HIGH NOISE IMMUNITY

V NIH =V NIL =28%V CC (MIN.)

I CC =4

A (MAX.) AT T A =25

. OUTPUT DRIVE CAPABILITY

. SYMMETRICAL OUTPUT IMPEDANCE

|I OH |=I OL = 4 mA (MIN.)

10 LSTTL LOADS

B1R

(Plastic Package)

F1R

(Ceramic Package)

. BALANCED PROPAGATION DELAYS

. WIDE OPERATING VOLTAGE RANGE

V CC (OPR) = 2 V TO 6 V

t PLH =t PHL

. PIN AND FUNCTION COMPATIBLE WITH

M1R

(Micro Package)

C1R

(Chip Carrier)

54/74LS192-193

ORDER CODES :

M54HCXXXF1R

M74HCXXXM1R

DESCRIPTION

M74HCXXXB1R

M74HCXXXC1R

The M54/74HC192/193 are a high speed CMOS SYN-

CHRONOUS UP/DOWN DECADE COUNTERS fab-

ricated in silicon gate C 2 MOS technology. They have

the same high speed performance of LSTTL combined

with true CMOS low power consumption. The counter

has two separate clock inputs, an UP COUNT input

and a DOWN COUNT input. All outputs of the flip-flop

are simultaneously triggered on the low to high transi-

tion of either clock while the other input is held high. The

direction of counting is determined by which input is

clocked. This counter may be preset by entering the

desired data on the DATA A, DATA B, DATA C, and

DATA D input. When the LOAD input is taken low the

data is loaded independently of either clock input. This

feature allows the counters to be used as divide-by-n

counters by modifying the count length with the preset

inputs. In addition the counter can also be cleared. This

is accomplished by inputting a high on the CLEAR

input. All 4 internal stages are set to low independently

of either COUNT input. Both a BORROW and CARRY

output are provided to enable cascading of both up and

down counting functions. The BORROW output pro-

duces a negative going pulse when the counter under-

flows and the CARRY outputs a pulse when the

counter overflows. The counter can be cascaded by

connecting the CARRY and BORROW outputs of one

device to the COUNT UP and COUNT DOWN inputs,

respectively, of the next device. All inputs are equipped

with protection circuits against static discharge and

transient excess voltage.

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

October 1992

1/15

. LOW POWER DISSIPATION

M54/M74HC192/193

INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

PIN No

SYMBOL NAME AND FUNCTION

3, 2, 6, 7

QA to QD Flip-Flop Outputs

CP D

Count Down Clock Input

CP U

Count Up Clock Input

LOAD

Asynchronous Parallel

Load Input (Active LOW)

CARRY

Count Up (Carry)

Output (Active LOW)

BORROW Count Down (Borrow)

Output (Active LOW)

CLEAR

Asynchronous Reset

Input (Active HIGH)

15, 1, 10, 9

DA to DD Data Inputs

GND

Ground (0V)

V CC

Positive Supply Voltage

IEC LOGIC SYMBOL (HC191)

IEC LOGIC SYMBOL (HC193)

TRUTH TABLE

COUNT UP

COUNT DOWN

LOAD

CLEAR

FUNCTION

COUNT UP

NO COUNT

COUNT DOWN

NO COUNT

PRESET

RESET

X: Don’t Care

2/15

M54/M74HC192/193

LOGIC DIAGAM (HC192)

3/15

M54/M74HC192/193

LOGIC DIAGAM (HC193)

4/15

M54/M74HC192/193

TIMING DIAGRAM (HC192)

TIMING DIAGRAM (HC193)

5/15

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika: