DAC0832.PDF

February 1995

DAC0830/DAC0831/DAC0832 8-Bit m P

Compatible, Double-Buffered D to A Converters

General Description

The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying

DAC designed to interface directly with the 8080, 8048,

8085, Z80 É , and other popular microprocessors. A deposit-

ed silicon-chromium R-2R resistor ladder network divides

the reference current and provides the circuit with excellent

temperature tracking characteristics (0.05% of Full Scale

Range maximum linearity error over temperature). The cir-

cuit uses CMOS current switches and control logic to

achieve low power consumption and low output leakage

current errors. Special circuitry provides TTL logic input volt-

age level compatibility.

Double buffering allows these DACs to output a voltage cor-

responding to one digital word while holding the next digital

word. This permits the simultaneous updating of any num-

ber of DACs.

The DAC0830 series are the 8-bit members of a family of

microprocessor-compatible DACs (MICRO-DAC TM ). For ap-

plications demanding higher resolution, the DAC1000 series

(10-bits) and the DAC1208 and DAC1230 (12-bits) are avail-

able alternatives.

Features

Y Double-buffered, single-buffered or flow-through digital

data inputs

Y Easy interchange and pin-compatible with 12-bit

DAC1230 series

Y Direct interface to all popular microprocessors

Y Linearity specified with zero and full scale adjust onlyÐ

NOT BEST STRAIGHT LINE FIT.

Y Works with g 10V reference-full 4-quadrant

multiplication

Y Can be used in the voltage switching mode

Y Logic inputs which meet TTL voltage level specs (1.4V

logic threshold)

Y Operates ``STAND ALONE'' (without m P) if desired

Y Available in 20-pin small-outline or molded chip carrier

package

Key Specifications

Y Current settling time

1 m s

Y Resolution

8 bits

Y Linearity

8, 9, or 10 bits

(guaranteed over temp.)

Y Gain Tempco

0.0002% FS/ § C

Y Low power dissipation

20 mW

BI-FET TM and MICRO-DAC TM are trademarks of National Semiconductor Corporation.

Z80 É is a registered trademark of Zilog Corporation.

Y Single power supply

5 to 15 V DC

Typical Application

*Allows easy upgrade to 12-bit DAC1230,

See application hints

TL/H/5608±1

Connection Diagrams (Top Views)

Dual-In-Line and

Small-Outline Packages

Molded Chip Carrier Package

This is necessary for the

12-bit DAC1230 series to

permit interchanging from

an 8-bit to a 12-bit DAC

with No PC board changes

and no software changes,

See applications section.

TL/H/5608±22

TL/H/5608±21

C 1995 National Semiconductor Corporation

TL/H/5608

RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings (Notes1&2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage (V CC )

Lead Temperature (soldering, 10 sec.)

Dual-In-Line Package (plastic)

260 § C

Dual-In-Line Package (ceramic)

300 § C

17 V DC

Surface Mount Package

Vapor Phase (60 sec.)

215 § C

Voltage at Any Digital Input

V CC to GND

Infrared (15 sec.)

220 § C

Voltage at V REF Input

g 25V

Operating Conditions

Temperature Range T MIN s T A s T MAX

Part numbers with `LCN' suffix 0 § Cto a 70 § C

Part numbers with `LCWM' suffix 0 § Cto a 70 § C

Part numbers with `LCV' suffix 0 § Cto a 70 § C

Part numbers with `LCJ' suffix b 40 § Cto a 85 § C

Part numbers with `LJ' suffix b 55 § Cto a 125 § C

Voltage at Any Digital Input V CC to GND

Electrical Characteristics V REF e 10.000 V DC unless otherwise noted. Boldface limits apply over tempera-

ture, T MIN s T A s T MAX . For all other limits T A e 25 § C.

b 65 § Cto a 150 § C

Package Dissipation

at T A e 25 § C (Note 3)

500 mW

DC Voltage Applied to

I OUT1 or I OUT2 (Note 4)

b 100 mV to V CC

ESD Susceptability (Note 14)

800V

V CC e 4.75 V DC

V CC e 5V DC g 5%

V CC e 12 V DC g 5%

V CC e 15.75 V DC

See

to 15 V DC g 5% Limit

Parameter

Conditions

Note

Units

Tested

Typ

Design Limit

Limit

(Note 12)

(Note 6)

(Note 5)

CONVERTER CHARACTERISTICS

Resolution

bits

Linearity Error Max

Zero and full scale adjusted

4, 8

b 10V s V REF s a 10V

DAC0830LJ & LCJ

0.05

0.05 % FSR

DAC0832LJ & LCJ

0.2

0.2 % FSR

DAC0830LCN, LCWM & LCV

0.05

0.05 % FSR

DAC0831LCN

0.1

0.1 % FSR

DAC0832LCN, LCWM & LCV

0.2

0.2 % FSR

Differential Nonlinearity

Zero and full scale adjusted

4, 8

Max

b 10V s V REF sa 10V

DAC0830LJ & LCJ

0.1

0.1 % FSR

DAC0832LJ & LCJ

0.4

0.4 % FSR

DAC0830LCN, LCWM & LCV

0.1

0.1 % FSR

DAC0831LCN

0.2

0.2 % FSR

DAC0832LCN, LCWM & LCV

0.4

0.4 % FSR

Monotonicity

b 10V s V REF

LJ & LCJ

bits

sa 10V

LCN, LCWM & LCV

bits

Gain Error Max

Using Internal R fb

g 0.2 g 1

g 1 %FS

b 10V s V REF sa 10V

Gain Error Tempco Max

Using internal R fb

0.0002

0.0006

FS/ § C

Power Supply Rejection

All digital inputs latched high

V CC e 14.5V to 15.5V

0.0002 0.0025

11.5V to 12.5V

0.0006

FSR/V

4.5V to 5.5V

0.013 0.015

Reference Input Max

15 20

k X

Min

15 10

k X

Output Feedthrough Error V REF e 20 Vp-p, f e 100 kHz

mVp-p

All data inputs latched low

Storage Temperature Range

Electrical Characteristics V REF e 10.000 V DC unless otherwise noted. Boldface limits apply over tempera-

ture, T MIN s T A s T MAX . For all other limits T A e 25 § C. (Continued)

V CC e 4.75 V DC

V CC e 12 V DC g 5%

V CC e 15.75 V DC

See

to 15 V DC g 5% Limit

Parameter

Conditions

Note

Units

Tested

Typ

Design Limit

Limit

(Note 12)

(Note 6)

(Note 5)

CONVERTER CHARACTERISTICS (Continued)

Output Leakage I OUT1 All data inputs LJ & LCJ

100

Current Max

latched low LCN, LCWM & LCV

100

I OUT2 All data inputs LJ & LCJ

100

latched high LCN, LCWM & LCV

100

Output

I OUT1 All data inputs

Capacitance

I OUT2

latched low

115

I OUT1 All data inputs

130

I OUT2

latched high

DIGITAL AND DC CHARACTERISTICS

Digital Input Max Logic Low LJ

4.75V

0.6

Voltages

15.75V

0.8

LCJ

4.75V

0.7

V DC

LCJ

15.75V

0.8

LCN, LCWM, LCV

0.95

0.8

Min Logic High

LJ & LCJ

2.0

V DC

LCN, LCWM, LCV

1.9

2.0

Digital Input Max Digital inputs k 0.8V

Currents

LJ & LCJ

b 50 b 200

b 200

m A

LCN, LCWM, LCV

b 160

b 200

m A

Digital inputs l 2.0V

LJ & LCJ

0.1 a 10

a 10

m A

LCN, LCWM, LCV

a 8

a 10

Supply Current Max

LJ & LCJ

1.2

3.5

Drain

LCN, LCWM, LCV

1.7

2.0

V CC e 5V DC g 5%

Electrical Characteristics V REF e 10.000 V DC unless otherwise noted. Boldface limits apply over tempera-

ture, T MIN s T A s T MAX . For all other limits T A e 25 § C. (Continued)

V CC e 15.75 V DC

V CC e 12 V DC g 5%

V CC e 4.75 V DC

V CC e 5V DC

to 15 V DC g 5%

g 5%

See

Limit

Symbol Parameter

Conditions

Note

Tested Design

Tested Design Units

Typ

Limit

Limit Limit

(Note 12)

(Note 5)

(Note 6)

(Note 5) (Note 6)

AC CHARACTERISTICS

t s Current Setting V IL e 0V, V IH e 5V

1.0

m s

Time

t W Write and XFER V IL e 0V, V IH e 5V 11 100

250

375

600

Pulse Width Min

320

900 900

t DS Data Setup Time V IL e 0V, V IH e 5V

100

250

375

600

Min

320

900 900

t DH Data Hold Time V IL e 0V, V IH e 5V

Min 30 50

t CS Control Setup Time V IL e 0V, V IH e 5V 9 110 250 600 900

Min 320 320 1100 1100

t CH Control Hold Time V IL e 0V, V IH e 5V 9 0 0 10 0 0

Min 0 0

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating

the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.

Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T JMAX , i JA , and the ambient temperature, T A . The maximum

allowable power dissipation at any temperature is P D e (T JMAX b T A )/ i JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this

device, T JMAX e 125 § C (plastic) or 150 § C (ceramic), and the typical junction-to-ambient thermal resistance of the J package when board mounted is 80 § C/W. For

the N package, this number increases to 100 § C/W and for the V package this number is 120 § C/W.

Note 4: For current switching applications, both I OUT1 and I OUT2 must go to ground or the ``Virtual Ground'' of an operational amplifier. The linearity error is

degraded by approximately V OS d V REF . For example, if V REF e 10Vthena1mVoffset, V OS ,onI OUT1 or I OUT2 will introduce an additional 0.01% linearity error.

Note 5: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.

Note 7: Guaranteed at V REF eg 10 V DC and V REF eg 1V DC .

Note 8: The unit ``FSR'' stands for ``Full Scale Range.'' ``Linearity Error'' and ``Power Supply Rejection'' specs are based on this unit to eliminate dependence on a

particular V REF value and to indicate the true performance of the part. The ``Linearity Error'' specification of the DAC0830 is ``0.05% of FSR (MAX)''. This

guarantees that after performing a zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within

0.05% c V REF of a straight line which passes through zero and full scale.

Note 9: Boldface tested limits apply to the LJ and LCJ suffix parts only.

Note 10: A 100nA leakage current with R fb e 20k and V REF e 10V corresponds to a zero error of (100 c 10 b 9 c 20 c 10 3 ) c 100/10 which is 0.02% of FS.

Note 11: The entire write pulse must occur within the valid data interval for the specified t W ,t DS ,t DH , and t S to apply.

Note 12: Typicals are at 25 § C and represent most likely parametric norm.

Note 13: Human body model, 100 pF discharged through a 1.5 k X resistor.

Switching Waveform

TL/H/5608±2

Definition of Package Pinouts

Co ntrol Signals (All control signals level act uated)

CS: Chip Select (active low) . Th e CS in combina-

tion with ILE will enable WR 1 .

ILE: Input Latch Ena ble (active high). The ILE in

combination with CS e nable s WR 1 .

WR 1 : Write 1. The active low WR 1 is used to load the

digital input data bits (DI) into the input l atch.

The data in the input latch is latche d w hen WR 1

is high. To update the input latchÐCS and WR 1

must be low while ILE is high.

WR 2 : Writ e 2 (a ctive low). This signal, in combination

with XFER, causes the 8-bit data which is avail-

able in the input latch to transfer to the DAC

XFER: Trans fer contro l sig nal (active low). The

XFER will enable WR 2 .

Other Pin Functions

DI 0 -DI 7 : Digital Inputs. DI 0 is the least significant bit

(LSB) and DI 7 is the most significant bit (MSB).

I OUT1 : DAC Current Output 1. I OUT1 is a maximum

for a digital code of all 1's in the DAC register,

and is zero for all 0's in DAC register.

I OUT2 : DAC Current Output 2. I OUT2 is a constant

minus I OUT1 ,orI OUT1 a I OUT2 e constant (I full

scale for a fixed reference voltage).

feedback resistor for the external op amp which is

used to provide an output voltage for the DAC.

This on-chip resistor should always be used (not

an external resistor) since it matches the resistors

which are used in the on-chip R-2R ladder and

tracks these resistors over temperature.

V REF : Reference Voltage Input. This input connects an

external precision voltage source to the internal R-

2R ladder. V REF can be selected over the range of

a 10 to b 10V. This is also the analog voltage in-

put for a 4-quadrant multiplying DAC application.

V CC : Digital Supply Voltage. This is the power supply

pin for the part. V CC can be from a 5to a 15V DC .

Operation is optimum for a 15V DC .

GND: The pin 10 voltage must be at the same ground

potential as I OUT1 and I OUT2 for current switching

applications. Any difference of potential (V OS pin

10) will result in a linearity change of

V OS pin 10

3V REF

For example, if V REF e 10V and pin 10 is 9mV

offset from I OUT1 and I OUT2 the linearity change

will be 0.03%.

Pin 3 can be offset g 100mV with no linearity

change, but the logic input threshold will shift.

R fb :

Feedback Resistor. The feedback resistor is

provided on the IC chip for use as the shunt

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