DS1075.PDF

DS1075

EconOscillator/Divider

FEATURES

•

PIN ASSIGNMENT

Dual Fixed frequency outputs (200 KHz – 100 MHz)

•

User–programmable on–chip dividers (from 1 – 513)

I/O

OUT0

V CC

GND

OSCIN

XTAL

PDN/SELX

•

User–programmable on–chip prescaler (1, 2, 4)

No external components

• ± 0.5% Initial tolerance

• ± 1% variation over temperature and voltage

•

DS1075Z 150–MIL SOIC

DS1075M 300–MIL DIP

Internal clock, External clock or crystal reference

options

FREQUENCY OPTIONS

Part No.

Max O/P freq.

•

Single 5V supply

DS1075–100

100 MHz

DS1075–80

80 MHz

•

Power–down mode

DS1075–66

66 MHz

DS1075–60

60 MHz

•

Synchronous output gating

DESCRIPTION

The DS1075 is a fixed frequency oscillator requiring no

external components for operation. Numerous operat-

ing frequencies are possible in the range 0.2 to 100 MHz

through the use of an on–chip programmable prescaler

and divider.

grammed devices can be ordered on a custom basis as

DS1075C–xxx. As alternatives to the on–board oscilla-

tor an external clock signal or a crystal may be used as a

reference. The choice of reference source (internal or

external) is user–selectable at the time of programming

(or on the fly if the SEL mode is chosen).

The DS1075 features a master oscillator followed by a

prescaler and then a programmable divider. The pres-

caler and programmable divider are user–program-

mable with the desired values being stored in non–vola-

tile memory. This allows the user to buy an off the shelf

component and program it on site prior to board produc-

tion. Design changes can be readily accommodated by

programming, or reprogramming, the desired values

into the on–chip non–volatile registers. An evaluation

board, DS1075K is available to simplify this task.

The DS1075 features a dual–purpose Input/Output pin.

If the device is powered up in Program mode this pin can

be used to input serial data to the on chip registers. After

a Write command this data is stored in non–volatile

memory. When the chip is subsequently powered up in

operating mode these values are automatically restored

to the on–chip registers and the Input/Output pin

becomes the oscillator output.

The DS1075 is shipped from the factory configured for

half the maximum operating frequency. Pre–pro-

The DS1075 is available in 8–pin DIP or SOIC pack-

ages, allowing the generation of a clock signal easily,

economically and using minimal board area.

021798 1/16

•

DS1075

BLOCK DIAGRAM Figure 1

PART NO.

SUFFIX

INTOSC

FREQUENCY

INTERNAL

OSCILLATOR

–100

–80

–66

–60

100 MHz

80 MHz

66 MHz

60 MHz

OSCIN

INTOSC

XTAL

rst

MSEL

sel

INTCLK

EXTCLK

E/I

sel

OUT0

MCLK

EN0

PROGRAMMABLE

DIVIDER

÷ N

rst

DIV1

sel

PDN

pden

OUTPUT

ENABLE

ENABLING

SEQUENCER

PDN/SELX

POWER

RESET

IN/OUT

I/O

CONT.

SIGNAL PATH

CONTROL PATH

BUS

021798 2/16

DS1075

PIN DESCRIPTIONS

Input/Output Pin (IN/OUT): This pin is the main oscilla-

tor output, with a frequency determined by clock refer-

ence, M and N dividers. Except in programming mode

this pin is always an output and will be referred to as

“OUT”. In programming mode this pin will be referred to

as “IN”.

much less than if OE is used because the internal oscil-

lator (if used) is completely powered down. Even if an

external reference or a crystal is used all of the on–chip

buffers are powered down to minimize current drain.

Consequently the device will take considerably longer

to recover (i.e., achieve stable oscillation) from a pow-

er–down condition than if the OE is used.

External Oscillator Input (OSCIN): This pin can be

used to supply an external reference frequency to the

device.

If the Select function is chosen (PDN bit = 0) this pin can

be used to switch between the internal oscillator and an

external reference (or crystal) on the fly. When this

mode is chos en the E/I select bit is overridden, a high

logic level on SELX will select the internal oscillator, a

low logic level will select the external reference (or crys-

tal oscillator).

Crystal Oscillator Connection (XTAL): A crystal can

be connected between this pin and OSCIN to provide an

alternative frequency reference. If a crystal is not used

this pin should be left open.

Output Enable Function (OE pin): The DS1075 also

features a “synchronous” output enable. When OE is at

a high logic level the oscillator free runs. When this pin is

taken low OUT is held low, immediately if OUT is already

low, or at it’s next high–to–low transition if OUT is high.

This prevents any possible truncation of the output

pulse width when the enable is used. While the output is

disabled the master oscillato r con tinues to run (produc-

ing an output at OUT0, if the EN0 bit = 0) but the internal

counters (/N) are reset. This results in a constant phase

relationship between OE’s return to a high level and the

resulting OUT signal. When the enable is released OUT

will make its first transition within one to two clock peri-

ods of the master clock.

Reference Output (OUT0 pin): A reference output,

OUT0, is also available from the output of the reference

select mux. This output is especially useful as a buffered

output of a crystal defined master frequency. OUT0 is

unaffected by the OE pin, but is disabled in a glitchless

fashion if the device is powered down. If this output is

not requ ired it can be permanently disabled by setting

the EN0 bit to one, and there will be a corresponding

reduction in overall power consumption.

USER–PROGRAMMABLE REGISTERS

The following registers can be programmed by the user

to determine operating frequency and mode of opera-

tion. Details of how these registers are programmed can

be found in a later section, in this section the function of

the registers are described. The register settings are

non–volatile, the values being stored automatically in

EEPROM when the registers are programmed.

Power–Down/Select Function ( PDN/SELX pin): The

Power–Down/Select (PDN/SELX) pin has a user–se-

lectable function determined by one bit (PDN bit) of the

user–programmable memory. According to whi ch fun c-

tion is selected, this pin will be referred to as PDN or

SELX.

Note: The register bits cannot be used to make mode or

frequency changes on the fly. Changes can only be

made by powering the device up in “Programming”

mode. For them to be become effective the device must

then be powered down and powered up again in

“Operation” mode.

If the Power–Down function is selected (PDN bit = 1) a

low logic level on this pin can be used to make the device

stop oscillating (active low) and go into a reduced power

consumption state. The “Enabling Sequencer” circuitry

will first disable OUT in the same way as when OE is

used. Next OUT0 will be disabled in a similar fashion.

Finally the oscillator circuitry will be disabled. In this

mode both outputs will go into a high impedance state.

The power consumption in the power–down state is

For programming purposes the register bits are divided

into two 9–bit words, the “MUX” word determines mode

of operation and prescaler values. The “DIV” word sets

the value of the programmable divider.

021798 3/16

DS1075

MUX WORD Figure 2

(MSB)

(LSB)

EN0

PDN

MSEL

DIV1

E/I

* These bits must be set to zero

E/I

This bit selects either the internal oscillator or the exter-

nal/crystal reference.

1=External/Crystal

0=Internal Oscillator

however, if the PDN bit is set to zer o the E/I bi t will be

overridden by the logic level on the PDN/SELX pin.

Table 1

PDN

BIT

E/I

PDN/SELX

OSCILLATOR

MODE

EXTERNAL/CRYSTAL

INTERNAL

POWER–DOWN

INTERNAL

EXTERNAL/CRYSTAL

DIV1

This bit allows the master clock to be routed directly to

the output (DIV1=1). The N programmable divider is

bypassed so the programmed value of N is ignored. The

frequency of the output (f OUT ) will be INTCLK or

EXTCLK depending on which reference has been

selected. If the Internal clock is selected the M prescaler

is also bypassed (the bit values of MSEL and M are

ignored) so in this case f OUT =INTOSC (which also

equals MCLK and INTCLK). If DIV1=0 the prescaler

and programmable divider function normally.

MSEL

This bit deter mines whether or not the M prescaler is

bypass ed. MSEL=1 will bypass the prescaler.

MSEL=0 will switch in the prescaler (unless overridden

by DIV1=1), with a divide–by number determined by the

M bit.

This bit sets the divide–by number for the prescaler.

M=0 results in divide–by–4, M=1 results in divide–by–2.

The se tting of this bit is irrelevant if either DIV1=1 or

MSEL=1.

Table 2

DIV1

BIT

E/I

BIT*

MSEL

BIT

OPERATION

INTERNAL OSCILLATOR DIVIDED BY 4*N

INTERNAL OSCILLATOR DIVIDED BY 2*N

INTERNAL OSCILLATOR DIVIDED BY N

EXTERNAL OSCILLATOR DIVIDED BY N

INTERNAL OSCILLATOR DIVIDED BY 1

EXTERNAL OSCILLATOR DIVIDED BY 1

*Assuming PDN bit = 1, otherwise internal/external selection will be controlled by the PDN/SELX pin.

DIV WORD Figure 3

(MSB)

(LSB)

N (9–BITS)

021798 4/16

DS1075

PDN

This b it is used to deter mine t he fun ction of the PDN/

SELX pin. If PDN=0, the PDN/SELX pin can be used to

determine the timing reference (either the internal oscil-

lator or an external reference/crystal). If PDN=1, the

PDN/SELX pin is used to put the device into power–

down mode.

INTOSC/(M*N) must be greater than f OUTmin ; if the

external clock is selected, EXTCLK/N must be greater

than f OUTmin . (If DIV1=1, then INTOSC or EXTCLK, as

applicable, must exceed f OUTmin ).

OPERATION OF OUTPUT ENABLE

Since the output enable, internal master oscillator

and/or external master oscillator are likely all asynchro-

nous there is the possibility of timing difficulties in the

application. To minimize these difficulties the DS1075

features an “enabling sequencer” to produce predict-

able results when the device is enabled and disabled. In

particular the output gating is configured so that trun-

cated output pulses can never be produced.

EN0

This bit is use d to d etermine whether the OUT0 pin is

active or not. I f EN0 =1, OUT0 is disabled (High–imped-

ance). If EN0=0, the internal reference clock (MCLK) is

output from OUT0. The OE pin has no effect on OUT0,

but OUT0 is disabled as part of the power–down

sequence.

These nine bits determine the value of the program-

mable divider. The range of divisor values is from 2 to

513, and is equal to the programmed value of N plus 2:

Enable timing

The output enable function is produced by sampling the

OE input with the output from the prescaler mux (MCLK)

and gating this with the output from the programmable

divider. The exact behavior of the device is therefore

dependent on the setup time (t SU ) from a transition on

the OE input to the rising edge of MCLK. If the actual

setup time is less than t SUEM then one more complete

cycle of MCLK will be required to complete the enable or

disable operation (see diagrams). This is unlikely to be

of any consequence in most applications, and then only

if the value for N is small. In general, the output will make

its first positive transition between approximately one

and two clock periods of MCLK after the rising edge

of OE.

Table 3

BIT

VALUES

DIVISOR (N)

VALUE

000000000

000000001

111111111

513

NOTE:

The maximum value of N is constrained by the minimum

output frequency. If the internal clock is selected,

FIGURE 4

t M

MCLK

t M = PERIOD OF MCLK

t d = PROP DELAY FROM MCLK = TO OUT =

MAX VALUE OF t en = t SUEM + 2 t M + t d

MIN VALUE OF t en = t SUEM + t M + t d

t SU

t d

OUT

t en

021798 5/16

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