L6203.PDF
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DMOS FULL BRIDGE DRIVER
L6201
L6202 - L6203
DMOS FULL BRIDGE DRIVER
SUPPLY VOLTAGE UP TO 48V
5A MAX PEAK CURRENT (2A max. for L6201)
TOTAL RMS CURRENT UP TO
L6201: 1A; L6202: 1.5A; L6203/L6201PS:4A
R
DS (ON)
0.3
W
(typical value at 25
°
C)
CROSS CONDUCTION PROTECTION
TTL COMPATIBLE DRIVE
OPERATING FREQUENCY UP TO 100 KHz
THERMAL SHUTDOWN
INTERNAL LOGIC SUPPLY
HIGH EFFICIENCY
MULTIPOWER BCD TECHNOLOGY
Powerdip 12+3+3
SO20 (12+4+4)
Multiwatt11
PowerSO20
DESCRIPTION
The I.C. is a full bridge driver for motor control ap-
plications realized in Multipower-BCD technology
which combines isolated DMOS power transistors
with CMOS and Bipolar circuits on the same chip.
By using mixed technology it has been possible to
optimize the logic circuitry and the power stage to
achieve the best possible performance. The
DMOS output transistors can operate at supply
voltages up to 42V and efficiently at high switch-
ORDERING NUMBERS:
L6201
(SO20)
L6201PS
(PowerSO20)
L6202
(Powerdip18)
L6203
(Multiwatt)
ing speeds. All the logic inputs are TTL, CMOS
and
m
C compatible. Each channel (half-bridge) of
the device is controlled by a separate logic input,
while a common enable controls both channels.
The I.C. is mounted in three different packages.
BLOCK DIAGRAM
July 1997
1/20
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L6201 - L6202 - L6203
PIN CONNECTIONS
(Top view)
SO20
POWERDIP
GND
1
20
GND
N.C.
2
19
18
N.C.
N.C.
OUT2
3
N.C.
4
17
ENABLE
V
S
5
16
SENSE
Vref
OUT1
6
15
BOOT1
IN1
7
14
BOOT2
8
9
13
IN2
N.C.
12
N.C.
GND
10
11
GND
D95IN216
PowerSO20
MULTIWATT11
2/20
L6201 - L6202 - L6203
PINS FUNCTIONS
Device
Name
Function
L6201 L6201PS L6202
L6203
1
16
1
10
SENSE A resistor R
sen se
connected to this pin provides feedback for
motor current control.
2
17
2
11
ENAB
LE
When a logic high is present on this pin the DMOS POWER
transistors are enabled to be selectively driven by IN1 and IN2.
3
2,3,9,12,
18,19
3
N.C.
Not Connected
4,5
–
4
GND
Common Ground Terminal
–
1, 10
5
6
GND
Common Ground Terminal
6,7
–
6
GND
Common Ground Terminal
8
–
7
N.C.
Not Connected
9
4
8
1
OUT2
Ouput of 2nd Half Bridge
10
5
9
2
V
s
Supply Voltage
11
6
10
3
OUT1
Output of first Half Bridge
12
7
11
4
BOOT1 A boostrap capacitor connected to this pin ensures efficient
driving of the upper POWER DMOS transistor.
13
8
12
5
IN1
Digital Input from the Motor Controller
14,15
–
13
GND
Common Ground Terminal
–
11, 20
14
6
GND
Common Ground Terminal
16,17
–
15
GND
Common Ground Terminal
18
13
16
7
IN2
Digital Input from the Motor Controller
19
14
17
8
BOOT2 A boostrap capacitor connected to this pin ensures efficient
driving of the upper POWER DMOS transistor.
20
15
18
9
V
ref
Internal voltage reference. A capacitor from this pin to GND is
recommended. The internal Ref. Voltage can source out a
current of 2mA max.
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
s
Power Supply
52
V
V
OD
Differential Output Voltage (between Out1 and Out2)
60
V
V
IN
,V
EN
Input or Enable Voltage
– 0.3 to + 7
V
I
o
Pulsed Output Current for L6201PS/L6202/L6203 (Note 1)
– Non Repetitive (< 1 ms) for L6201
for L6201PS/L6202/L6203
5
5
10
1
A
A
A
A
DC Output Current
for L6201 (Note 1)
V
sense
Sensing Voltage
– 1 to + 4
V
V
b
Boostrap Peak Voltage
60
V
P
tot
Total Power Dissipation:
T
pins
=90
°
C for L6201
for L6202
4
5
20
0.9
1.3
2.3
W
W
W
W
W
W
T
case
=90
°
C for L6201PS/L6203
T
amb
=70
°
C for L6201 (Note 2)
for L6202 (Note 2)
for L6201PS/L6203 (Note 2)
T
stg
,T
j
Storage and Junction Temperature
– 40 to + 150
C
Note 1:
Pulse width limited only by junction temperature and transient thermal impedance (see thermal characteristics)
Note 2:
Mounted on board with minimized dissipating copper area.
3/20
°
L6201 - L6202 - L6203
THERMAL DATA
Symbol
Parameter
Value
Unit
L6201
L6201PS
L6202
L6203
Rt
h j-pins
Rt
h j-case
Rt
h j-amb
Thermal Resistance Junction-pins
max
15
–
85
–
–
13 (*)
12
–
60
–
3
35
Thermal Resistance Junction Case
max.
°
C/W
Thermal Resistance Junction-ambient
max.
(*) Mounted on aluminium substrate.
ELECTRICAL CHARACTERISTICS
(Refer to the Test Circuits; T
j
=25
°
C, V
S
= 42V, V
sens
= 0, unless
otherwise specified).
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
s
Supply Voltage
12
36
48
V
V
ref
Reference Voltage
I
REF
= 2mA
13.5
V
I
REF
Output Current
2
A
I
s
Quiescent Supply Current
EN = H V
IN
=L
EN = H V
IN
=H
EN = L ( Fig. 1,2,3)
I
L
=0
10
10
8
15
15
15
mA
mA
mA
f
c
Commutation Frequency (*)
30
100
KHz
T
j
Thermal Shutdown
150
°
C
T
d
Dead Time Protection
100
ns
TRANSISTORS
OFF
I
DSS
Leakage Current
Fig. 11 V
s
=52V
1
mA
ON
R
DS
On Resistance
Fig. 4,5
0.3
0.55
W
V
DS(ON)
Drain Source Voltage
Fig. 9
I
DS
=1A
I
DS
= 1.2A
I
DS
=3A
L6201
L6202
L6201PS/0
3
0.3
0.36
0.9
V
V
V
V
sens
Sensing Voltage
– 1
4
V
SOURCE DRAIN DIODE
V
sd
Forward ON Voltage
Fig. 6a and b
I
SD
=1A
L6201
EN = L
I
SD
= 1.2A
L6202
EN = L
I
SD
=3A
L6201PS/03
EN =
L
0.9 (**)
0.9 (**)
1.35(**)
V
V
V
t
rr
Reverse Recovery Time
dif
dt
300
ns
=25A/
m
s
I
F
=1A
I
F
= 1.2A
I
F
=3A
L6201
L6202
L6203
t
fr
Forward Recovery Time
200
ns
LOGIC LEVELS
V
IN L
,V
EN L
Input Low Voltage
– 0.3
0.8
V
V
IN H
,V
EN H
Input High Voltage
2
7
V
I
IN L
,
EN L
Input Low Current
V
IN
,V
EN
= L
–10
m
A
I
IN H
,
EN H
Input High Current
V
IN
,V
EN
=H
30
m
A
4/20
L6201 - L6202 - L6203
ELECTRICAL CHARACTERISTICS
(Continued)
LOGIC CONTROL TO POWER DRIVE TIMING
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
1
(V
i
)
Source Current Turn-off Delay
Fig. 12
300
ns
t
2
(V
i
)
Source Current Fall Time
Fig. 12
200
ns
t
3
(V
i
)
Source Current Turn-on Delay
Fig. 12
400
ns
t
4
(V
i
)
Source Current Rise Time
Fig. 12
200
ns
t
5
(V
i
)
Sink Current Turn-off Delay
Fig. 13
300
ns
t
6
(V
i
)
Sink Current Fall Time
Fig. 13
200
ns
t
7
(V
i
)
Sink Current Turn-on Delay
Fig. 13
400
ns
t
8
(V
i
)
Sink Current Rise Time
Fig. 13
200
ns
(*)
Limited by power dissipation
(**)
In synchronous rectification the drain-source voltage drop VDS is shown in fig. 4 (L6202/03); typical value for the L6201 is of 0.3V.
Figure 1:
Typical Normalized I
S
vs. T
j
Figure 2:
Typical Normalized Quiescent Current
vs. Frequency
Figure 3:
Typical Normalized I
S
vs. V
S
Figure 4:
Typical R
DS (ON)
vs. V
S
~V
ref
5/20
Plik z chomika:
Kot_Maciek
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