L6569.PDF

L6569

L6569A

HIGH VOLTAGE HALF BRIDGE

DRIVER WITH OSCILLATOR

TECHNOLOGY: BCD ”OFF-LINE”

FLOATING SUPPLY VOLTAGE UP TO 600V

GND REFERRED SUPPLY VOLTAGE UP TO

18V

DRIVER CURRENT CAPABILITY:

- SINK CURRENT = 270mA

- SOURCE CURRENT = 170mA

VERY LOW START UP CURRENT: 150

Minidip

SO8

ORDERING NUMBERS:

L6569/L6569A

L6569D/L6569AD

50V/ns

DESCRIPTION

The device is a high voltage half bridge driver

with built-in oscillator. The frequency of the oscil-

lator can be programmed using external resistor

and capacitor.

The output drivers are designed to drive external

n-channel power MOSFET and IGBT. The inter-

nal logic assures a dead time to avoid cross-con-

duction of the power devices.

BLOCK DIAGRAM

H.V.

R HV

C VS

V S

BOOT

Source

CHARGE

PUMP

BIAS

REGULATOR

LEVEL

SHIFTER

HVG

C BOOT

V S

HIGH

SIDE

DRIVER

R F

BUFFER

OUT

LOAD

R F

C F

COMP

C F

V S

LOW SIDE

DRIVER

COMP

LOGIC

LVG

GND

D94IN058D

December 1997

1/10

VERY LOW OPERATING CURRENT: <2mA

UNDERVOLTAGE LOCKOUT

PROGRAMMABLE OSCILLATOR

FREQUENCY

dV/dt IMMUNITY UP TO

L6569/L6569A

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

I S

(*)

Supply Current

V CF

Oscillator Resistor Voltage

V LVG

Low Side Switch Gate Output

14.6

V OUT

High Side Switch Source Output

-1 to V BOOT -18

V HVG

High Side Switch Gate Output

-1 to V BOOT

V BOOT

Floating Supply Voltage

618

V BOOT/OUT

Floating Supply vs OUT Voltage

dV BOOT /dt

V BOOT Slew Rate (Repetitive)

V/ns

dV OUT /dt

V OUT Slew Rate (Repetitive)

V/ns

T stg

Storage Temperature

-40 to 150

T j

Junction Temperature

-40 to 150

T amb

Ambient Temperature (Operative)

-40 to 125

(*) The device has an internal zener clamp between GND and V S (typical 15.6V).

Therefore the circuit should not be driven by a DC low impedance power source.

Note: ESD immunity for pins 6, 7 and 8 is guaranteed up to 900 V (Human Body Model)

THERMAL DATA

Symbol

Parameter

Minidip

SO8

Unit

R th j-amb

Thermal Resistance Junction-Ambient

Max

100

150

C/W

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min.

Max.

Unit

V S

Supply Voltage

V CL

V BOOT

Floating Supply Voltage

500

V OUT

High Side Switch Source Output

-1

V BOOT -V CL

f out

Oscillation Frequency

200

kHz

PIN CONNECTION

V S

R F

BOOT

HVG

C F

GND

OUT

LVG

D94IN059

2/10

L6569/L6569A

ELECTRICAL CHARACTERISTICS (V S =12V;V BOOT -V OUT =12V;T j =25 ° C; unless otherwise specified.)

Symbol

Parameter

Test Condition

Min.

Typ.

Max. Unit

V SUVP

1 S Turn On Threshold

8.3

9.7

V SUVN

V S Turn Off Threshold

7.3

8.7

V SUVH

V S Hysteresis

0.7

1.3

V CL

V S Clamping Voltage

I S = 5mA

14.6

15.6

16.6

I SU

Start Up Current

V S <V SUVN

150

250

I q

Quiescent Current

V S >V SUVP

500

700

I BOOTLK

Leakage Current BOOT pin vs

GND

V BOOT = 580V

I OUTLK

Leakage Current OUT pin vs GND V OUT = 562V

I HVG SO

High Side Driver Source Current V HVG = 6V

110

175

I HVG SI

High Side Driver Sink Current

V HVG = 6V

190

275

I LVG SO

Low Side Driver Source Current V LVG = 6V

110

175

I LVG SI

Low Side Driver Sink Current

V LVG = 6V

190

275

V RFON

RF High Level Output Voltage

I RF = 1mA

V S -0.05

V S -0.2

V RF OFF

RF Low Level Output Voltage

I RF = -1mA

200

V CFU

CF Upper Threshold

7.7

7.95

8.2

V CFL

CF Lower Threshold

3.80

4.05

4.3

t d

Internal Dead Time

0.85

1.25

1.65

D C

Duty Cycle, Ratio Between

Dead Time + Conduction Time

of High Side and Low Side

Drivers

0.45

0.5

0.55

R ON

On resistance of Boostrap

LDMOS

120

V BC

Boostrap Voltage before UVLO

VS = 8.2

2.5

3.6

I AVE

Average Current from Vs

No Load, fs = 60KHz

1.2

1.5

fout

Oscillation Frequency

RT = 12k

CT = 1nF

kHz

OSCILLATOR FREQUENCY

The frequency of the internal oscillator can be

programmed using external resistor and capacitor.

The nominal oscillator frequency can be calcu-

lated using the following equation:

(see Block Diagram) and syncronized, with a 50

nsec delay, with the Low Side Gate driver (LVG

pin), actually working as a syncronous rectifier .

The charging path for the Bootstrap capacitor is

closed via the Lower External Mosfet that is

driven ON (i.e. LVG High) for a time interval:

f OSC

2 V R F V C F V In 2 =

1.3863 V R F V C F

T c =R F

V C F

V ln2 @ 1.1R F

V C F

where R F and C F are the external resistor and ca-

pacitor

starting from the time the Supply Voltage Vs has

reached the Turn On Voltage (Vsup = 9 V typical

value).

After time T1 (see Waveform Diagram) the

LDMOS that charges the Bootstrap Capacitor, is

on on with a Ron=120 ohm (typical value).

In the L6569A a different start up procedure is

followed (see Waveform Diagram). The Lower

External Mosfet is drive OFF untill Vs has

reached the Turn On Threshold (Vsuvp), then

again the Tc time interval starts as above.

Bootstrap Function

The L6569 has an internal Bootstrap structure

that enables the user to avoid the external diode

needed, in similar devices, to perform the charge

of the bootstrap capacitor that, in turns, provide

an appropriate driving to the Upper External Mos-

fet. The operation is achieved with an unique

structure (patented) that uses a High Voltage Lat-

eral DMOS driven by an internal charge pump

3/10

L6569/L6569A

Being the LDMOS used to implement the boot-

strap operation a ”bidirectional” switch the current

flowing into the Vboot pin can lead an undue

stress to the LDMOS itself if a ZERO VOLTAGE

SWITCHING operations is not ensured, and then

an high voltage is applied to the Vboot pin. This

condition can occur, for example, when the load

is removed and an high resistive value is placed

in series with the gate of the external Power Mos.

To help the user to secure his design a SAFE

OPERATING AREA for the Bootstrap LDMOS is

provided (fig. 6). Let’s consider the steps that

should be taken.

1) Calculate the Turn on delay (td) of your Lower

Power MOS:

t d = (Rg + Rid) V Ciss ln(1/(1-V TH /V S ))

Lower Power MOS (remember to add the Vs,

your Low Voltage Supply, value) on the Boot-

strap LDMOS SOA . On fig. 7 an example is

given where:

Vs = Low Voltage Supply

V HV = High Voltage Supply Rail

The Vboot voltage swing must fall below the

curve identified by the actual operating frequency

of your application.

DEMO BOARD

To allow an easy evaluation of the device, a P.C.

board dedicated to lamp ballast application has

been designed.

Fig.10 shows the electrical schematic of a typical

ballast application, while the PC and component

layout is given in Fig11. This application has been

designed to work with both the 110+/-20%V and

the 220 +/- 20%V mains by means of a voltage

doubler configuration at the bulk capacitor. The

ballast inductance and the operating frequency

are especially designed for a 18 W Sylvania De-

luxe T/E type bulb. The PTC for preheat at the

start up and the two back to back synchronization

diodes, makes this application easy to implement

and safe in operation.

2) Calculate the Fall time (tf) of your Lower

Power MOS:

tf = (V S -V TH ) / (Rg+Rid) V Qgd

where:

Rg= External gate resistor

Rid = 50 ohm , typical equivalent output resis-

tance of the driving buffer (when sourcing current)

V TH , Ciss and Qgd are Power MOS parameters

V S = Low Voltage Supply.

3) Sketch the Vboot waweform (using log-log

scales) starting from the Drain Voltage of the

Figure 1: WAVEFORMS (L6569)

V S

V SUVP

V BOOT -V OUT

V S

t =Ron*C BOOT

4.6V(typ)

V CF

LVG

T C

D95IN250B

4/10

L6569/L6569A

Figure 2: WAVEFORMS (L6569A)

V S

V SUVP

V BOOT -V OUT

V S

4.6V(typ)

=Ron*C BOOT

V CF

LVG

T C

D95IN251B

Figure 3: Typical Dead Time vs. Temperature

Dependency

Figure 4: Typical Frequency vs Temperature

Dependency

Dead time [

sec]

Frequency [KHz]

D96IN379A

1.7

D96IN378A

1.6

1.5

1.4

1.3

1.2

1.1

0.9

-50

100

150

-50 -25

75 100 125

Temperature [C]

5/10

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