OP07_AnalogDevices.pdf

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OP07 Ultralow Offset Voltage Operational Amplifier Data Sheet (REV. C)
a
Ultralow Offset Voltage
Operational Amplifier
OP07
FEATURES
Low V OS : 75
PIN CONNECTIONS
C Max
Ultrastable vs. Time: 1.5
V/
8-Lead PDIP (P-Suffix)
8-Lead SOIC (S-Suffix)
V/Month Max
V p-p Max
Wide Input Voltage Range:
14 V
Wide Supply Voltage Range: 3 V to 18 V
Fits 725,108A/308A, 741, AD510 Sockets
125
V OS T RIM
–IN
+IN
1
2
3
4
OP07
8
7
6
5
V OS T RIM
V+
OUT
NC
C Temperature-Tested Dice
V–
APPLICATIONS
Wireless Base Station Control Circuits
Optical Network Control Circuits
Instrumentation
Sensors and Controls
Thermocouples
RTDs
Strain Bridges
Shunt Current Measurements
Precision Filters
NC = NO CONNECT
high closed-loop gains. Stability of offsets and gain with time or
variations in temperature is excellent. The accuracy and stability
of the OP07, even at high gain, combined with the freedom
from external nulling have made the OP07 an industry standard
for instrumentation applications.
The OP07 is available in two standard performance grades. The
OP07E is specified for operation over the 0°C to 70°C range, and
the OP07C is specified over the –40°C to +85°C temperature range.
The OP07 is available in epoxy 8-lead PDIP and 8-lead SOIC. It
is a direct replacement for 725, 108A, and OP05 amplifiers;
741 types may be directly replaced by removing the 741’s nulling
potentiometer. For improved specifications, see the OP177 or
OP1177. For ceramic DIP and TO-99 packages and standard
micro circuit (SMD) versions, see the OP77.
V max for
OP07E) that is obtained by trimming at the wafer stage. These
low offset voltages generally eliminate any need for external null-
ing. The OP07 also features low input bias current (
µ
4 nA for the
OP07E) and high open-loop gain (200 V/mV for the OP07E).
The low offsets and high open-loop gain make the OP07 particu-
larly useful for high gain instrumentation applications.
The wide input voltage range of
±
13 V minimum combined with a
high CMRR of 106 dB (OP07E) and high input impedance pro-
vide high accuracy in the noninverting circuit configuration.
Excellent linearity and gain accuracy can be maintained even at
±
V+
7
R2A*
R2B*
*NOTE
R2A AND R2B ARE
ELECTRONICALLY
ADJUSTED ON CHIP
AT FACTORY FOR
MINIMUM INPUT
OFFSET VOLTAGE.
(OPTIONAL
NULL)
C1
R7
1
8
R1A
R1B
Q19
Q9
Q10
R9
Q7
Q8
Q11
Q12
OUTPUT
6
Q5
Q3 Q6
Q4
R3
C3
Q17
NONINVERTING
INPUT
Q 27
C2
R10
Q16
3
Q1
R5
Q21
Q22
Q23
Q24
Q 26
Q20
INVERTING
INPUT
R4
Q 25
Q15
Q2
2
Q14
Q18
4
Q13
R6
R8
V–
Figure 1. Simplified Schematic
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
V Max
Low V OS Drift: 1.3
Low Noise: 0.6
GENERAL DESCRIPTION
The OP07 has very low input offset voltage (75
713863567.022.png 713863567.023.png 713863567.024.png 713863567.025.png 713863567.001.png 713863567.002.png 713863567.003.png 713863567.004.png 713863567.005.png 713863567.006.png 713863567.007.png 713863567.008.png 713863567.009.png 713863567.010.png 713863567.011.png 713863567.012.png 713863567.013.png 713863567.014.png 713863567.015.png 713863567.016.png 713863567.017.png
OP07–SPECIFICATIONS
OP07E ELECTRICAL CHARACTERISTICS
Parameter
(V S =
15 V, T A = 25
C, unless otherwise noted.)
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Input Offset Voltage 1
V OS
30
75
µV
Long-Term V OS Stability 2
V OS /Time
0.3
1.5
µV/Mo
Input Offset Current
I OS
0.5
3.8
nA
Input Bias Current
I B
± 1.2
± 4.0
nA
Input Noise Voltage
e n p-p
0.1 Hz to 10 Hz 3
0.35
0.6
µV p-p
Input Noise Voltage Density
e n
f O = 10 Hz
10.3
18.0
nV/√
Hz
f O = 100 Hz 3
10.0
13.0
nV/√
Hz
f O = 1 kHz
9.6
11.0
nV/√
Hz
Input Noise Current
I n p-p
14
30
pA p-p
Input Noise Current Density
I n
f O = 10 Hz
0.32
0.80
pA/√
Hz
f O = 100 Hz 3
0.14
0.23
pA/√
Hz
f O = 1 kHz
0.12
0.17
pA/√
Hz
Input Resistance—Differential Mode 4
R IN
15
50
MΩ
Input Resistance—Common-Mode
R INCM
160
GΩ
Input Voltage Range
IVR
± 13
± 14
V
Common-Mode Rejection Ratio
CMRR
V CM = ± 13 V
106
123
dB
Power Supply Rejection Ratio
PSRR
V S = ± 3 V to ± 18 V
5
20
µV/V
Large Signal Voltage Gain
A VO
R L ≥ 2 kΩ, V O = ± 10 V
200
500
V/mV
R L ≥ 500 Ω, V O = ± 0.5 V,
V S = ± 3 V 4
150
400
V/mV
OUTPUT CHARACTERISTICS
Output Voltage Swing
V O
R L
≥
10 k
Ω
±
12.5
±
13.0
V
R L
≥
2 k
Ω
±
12.0
±
12.8
V
R L
≥
1 k
Ω
±
10.5
±
12.0
V
DYNAMIC PERFORMANCE
Slew Rate
SR
R L ≥ 2 kΩ
3
0.1
0.3
V/µs
Closed-Loop Bandwidth
BW
A VOL = 1 5
0.4
0.6
MHz
Closed-Loop Output Resistance
R O
V O = 0, I O = 0
60
Ω
Power Consumption
P d
V S = ± 15 V, No Load
75
120
mW
V S = ± 3 V, No Load
4
6
mW
Offset Adjustment Range
R P = 20 kΩ
± 4
mV
NOTES
1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
2 Long-term input offset voltage stability refers to the averaged trend time of V OS vs. the time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in V OS during the first 30 operating days are typically 2.5
µ
V, refer to the typical performance characteristics. Parameter is sample tested.
–2–
REV. C
3 Sample tested.
4 Guaranteed by design.
5 Guaranteed but not tested.
Specifications subject to change without notice.
713863567.018.png
OP07
OP07C ELECTRICAL CHARACTERISTICS
Parameter
(V S =
15 V, T A = 25
C, unless otherwise noted.)
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Input Offset Voltage 1
V OS
60
150
µV
Long-Term V OS Stability 2
V OS /Time
0.4
2.0
µV/Mo
Input Offset Current
I OS
0.8
6.0
nA
Input Bias Current
I B
± 1.8
± 7.0
nA
Input Noise Voltage
e n p-p
0.1 Hz to 10 Hz 3
0.38
0.65
µV p-p
Input Noise Voltage Density
e n
f O = 10 Hz
10.5
20.0
nV/√
Hz
f O = 100 Hz 3
10.2
13.5
nV/√
Hz
f O = 1 kHz
9.8
11.5
nV/√
Hz
Input Noise Current
I n p-p
15
35
pA p-p
Input Noise Current Density
I n
f O = 10 Hz
0.35
0.90
pA/√
Hz
f O = 100 Hz 3
0.15
0.27
pA/√
Hz
f O = 1 kHz
0.13
0.18
pA/√
Hz
Input Resistance—Differential Mode 4
R IN
8
33
MΩ
Input Resistance—Common-Mode
R INCM
120
GΩ
Input Voltage Range
IVR
± 13
± 14
V
Common-Mode Rejection Ratio
CMRR
V CM = ± 13 V
100
120
dB
Power Supply Rejection Ratio
PSRR
V S = ± 3 V to ± 18 V
7
32
µV/V
Large Signal Voltage Gain
A VO
R L ≥ 2 kΩ, V O = ± 10 V
120
400
V/mV
R L ≥ 500 Ω, V O = ± 0.5 V,
V S = ± 3 V 4
100
400
V/mV
OUTPUT CHARACTERISTICS
Output Voltage Swing
V O
R L
≥
10 k
Ω
±
12.0
±
13.0
V
R L
≥
2 k
Ω
±
11.5
±
12.8
V
R L
≥
1 k
Ω
±
12.0
V
DYNAMIC PERFORMANCE
Slew Rate
SR
R L ≥ 2 kΩ
3
0.1
0.3
V/µs
Closed-Loop Bandwidth
BW
A VOL = 1 5
0.4
0.6
MHz
Closed-Loop Output Resistance
R O
V O = 0, I O = 0
60
Ω
Power Consumption
P d
V S = ± 15 V, No Load
80
150
mW
V S = ± 3 V, No Load
4
8
mW
Offset Adjustment Range
R P = 20 kΩ
± 4
mV
NOTES
1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
2 Long-term input offset voltage stability refers to the averaged trend time of V OS vs. the time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in V OS during the first 30 operating days are typically 2.5
V, refer to the typical performance characteristics. Parameter is sample tested.
REV. C
–3–
µ
3 Sample tested.
4 Guaranteed by design.
5 Guaranteed but not tested.
Specifications subject to change without notice.
713863567.019.png
OP07–SPECIFICATIONS
OP07E ELECTRICAL CHARACTERISTICS
Parameter
(V S =
15 V, 0
C
T A
70
C, unless otherwise noted.)
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Input Offset Voltage 1
V OS
45
130
µV
Voltage Drift without External Trim 2
TCV OS
0.3
1.3
µV/°C
Voltage Drift with External Trim 3
TCV OSN
R P = 20 kΩ
0.3
1.3
µV/°C
Input Offset Current
I OS
0.9
5.3
nA
Input Offset Current Drift
TCI OS
8
35
pA/°C
Input Bias Current
I B
± 1.5
± 5.5
nA
Input Bias Current Drift
TCI B
13
35
pA/°C
Input Voltage Range
IVR
± 13
± 13.5
V
Common-Mode Rejection Ratio
CMRR
V CM = ± 13 V
103
123
dB
Power Supply Rejection Ratio
PSRR
V S = ± 3 V to ± 18 V
7
32
µV/V
Large Signal Voltage Gain
A VO
R L ≥ 2 kΩ, V O = ± 10 V
180
450
V/mV
OUTPUT CHARACTERISTICS
Output Voltage Swing
V O
R L
≥
10 k
Ω
±
12
±
12.6
V
NOTES
1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
2 Guaranteed by design.
3 Sample tested.
Specifications subject to change without notice.
OP07C ELECTRICAL CHARACTERISTICS
Parameter
(V S = 15 V, 40 C T A 85 C, unless otherwise noted.)
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Input Offset Voltage 1
V OS
85
250
µ
V
Voltage Drift without External Trim 2
TCV OS
0.5
1.8
µ
V/
°
C
Voltage Drift with External Trim 3
TCV OSN
R P = 20 k
Ω
0.4
1.8
µ
V/
°
C
Input Offset Current
I OS
1.6
8.0
nA
Input Offset Current Drift
TCI OS
12
50
pA/
°
C
Input Bias Current
I B
±
2.2
±
9.0
nA
Input Bias Current Drift
TCI B
18
50
pA/
°
C
Input Voltage Range
IVR
±
13
±
13.5
V
Common-Mode Rejection Ratio
CMRR
V CM =
±
13 V
97
120
dB
Power Supply Rejection Ratio
PSRR
V S =
±
3 V to
±
18 V
10
51
µ
V/V
Large Signal Voltage Gain
A VO
R L
≥
2 k
Ω
, V O =
±
10 V
100
400
V/mV
OUTPUT CHARACTERISTICS
Output Voltage Swing
V O
R L ≥ 10 kΩ
± 11
± 12.6
V
NOTES
1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
2 Guaranteed by design.
3 Sample tested.
Specifications subject to change without notice.
–4–
REV. C
713863567.020.png
OP07
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage (V S ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 22 V
Input Voltage 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 22 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 30 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range
S, P Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range
OP07E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
OP07C . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C
NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2 For supply voltages less than
Package Type
JA *
JC
Unit
8-Lead PDIP (P)
103
43
°C/W
8-Lead SOIC (S)
158
43
°C/W
*
JA is specified for worst-case conditions, i.e.,
JA is specified for device in socket
for PDIP package, and
JA is specified for device soldered to printed circuit board
for SOIC package.
±
22 V, the absolute maximum input voltage is equal
to the supply voltage.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
OP07EP 0°C to 70°C 8-Lead PDIP P-8
OP07CP –40°C to +85°C 8-Lead PDIP P-8
OP07CS –40°C to +85°C 8-Lead SOIC S-8
OP07CS-REEL –40°C to +85°C 8-Lead SOIC S-8
OP07CS-REEL7 –40°C to +85°C 8-Lead SOIC S-8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
OP07 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. C
–5–
713863567.021.png

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