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AVR091: Replacing AT90S2313 by ATtiny2313

Features

• AT90S2313 Errata Corrected in ATtiny2313

• Changes to Bit and Register Names

• Changes to Interrupt Vector

• Oscillators and Selecting Start-up Delays

• Improvements to Timer/Counters and Prescalers

• Improvements to the U(S)ART

• Enhanced Watchdog Timer

• Changes to EEPROM Writing

• Programming Interface

• Operational Voltage Ranges

• Changes to Electrical Characteristics

8-bit

Microcontrollers

Application Note

Introduction

This application note is a guide to help current AT90S2313 users convert existing

designs to ATtiny2313.

In addition to the differences described in this document, the electrical characteristics

of the devices are different. Check the datasheets for detailed information.

Improvements or added features in the AT90S2313 that are not in conflict with those

in AT90S1200 are not listed in this document.

Rev. 4298A–AVR–10/03

AT90S2313 Errata

Corrected in

ATtiny2313

The following items from the Errata Sheets of the AT90S2313 do not apply to the

ATtiny2313. Refer to the AT90S2313 Errata Sheet for more details.

Releasing Reset

Condition without Clock

ATtiny2313 has a new reset circuit, which for any External Reset Pulse exceeding the

minimum pulse width t RST causes an internal reset even though the condition disap-

pears before any valid clock is present.

Lock Bits at High V CC

In ATtiny2313, the Lock Bits can be cleared at any voltage level within the operating

range.

Reset During EEPROM

Write

In ATtiny2313, the erroneous behavior of the EEPROM address register is no longer an

issue. See the datasheet for general information about preventing EEPROM corruption.

Serial Programming at

Voltages below 2.9V

In relation to the serial programming there are no restrictions on the supply voltage or

system frequency as long as the device is operated within the voltage and frequency

range specified in the data sheet for the ATtiny2313.

UART Looses

Synchronization if RXD

Line is Low when UART

Receive is Disabled

The UART is replaced with a USART, which does not have this problem. The starting

edge of a reception is only accepted as valid if the Receive Enable bit in the USART

Control Register is set.

Changes to Names

The following control bits have changed names, but have the same functionality and

placement when accessed as in AT90S2313. These AT90S1200 bit definitions can

therefore be added to the ATtiny2313 definitions file, so no rewriting of the application

code is necessary.

Table 1. Changed Bit Names

Bit Name in AT90S2313

Bit Name in ATtiny2313

I/O Register (AT90S2313)

TICIE1

ICIE1

TIMSK

SM0

MCUCR

PWM10

WGM10

TCCR1A

PWM11

WGM11

TCCR1A

CTC1

WGM12

TCCR1B

WDTOE

WDCE

WDTCR

EEWE

EEPE

EECR

EEMWE

EEMPE

EECR

DOR

USR

CHR9

UCSZ2

UCR

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The following I/O Registers have changed names on ATtiny2313, but include the same

functionality and location when accessed as in AT90S2313.

Table 2. Changed Register Names

USR

UCSRA

UCR

UCSRB

UBRR

UBRRL

Changes to Interrupt

Vector

The interrupt vector table of the ATtiny2313 differs from the one of AT90S2313. These

changes mainly consist of addition of new interrupt vectors.

Table 3. Changes to Interrupt Vectors

Vector No.

Program Address

AT90S2313

ATtiny2313

0x0000

RESET

0x0001

INT0

0x0002

INT1

0x0003

TIMER1 CAPT1

TIMER1 CAPT

0x0004

TIMER1 COMP1

TIMER1 COMPA

0x0005

TIMER1 OVF1

TIMER1 OVF

0x0006

TIMER0 OVF0

TIMER0 OVF

0x0007

UART RX

USART0 RX

0x0008

UART UDRE

USART0 UDRE

0x0009

UART TX

USART0 TX

0x000A

ANA_COMP

ANALOG COMP

0x000B

PCINT

0x000C

TIMER1 COMPB

0x000D

TIMER0 COMPA

0x000E

TIMER0 COMPB

0x000F

USI START

0x0010

USI OVERFLOW

0x0011

EE READY

0x0012

WDT OVERFLOW

4298A–AVR–10/03

Oscillators and

Selecting Start-up

Delays

ATtiny2313 provides more Oscillators and Start-up Time options than AT90S2313.

The default clock source setting on ATtiny2313 is 1 MHz sourced from the Internal RC

Oscillator. The internal RC oscillator is set to run at 8 MHz, but with the system clock

prescaling preset to divide by 8. The default start-up delay is 65ms. There is no setting

that results in a 16ms startup delay; 4ms or 64ms must be selected.

Fuses must be programmed to enable the ATtiny2313 to use the XTAL1 and XTAL2

pins as clock source as on the AT90S2313. The correct fuse setting for ATtiny2313

depend on if the selected clock source is external clock or a crystal oscillator, and which

frequency it will be running at.

During wake-up from Power-down mode, the ATtiny2313 uses the CPU frequency to

determine the delay of the wake-up delay, while AT90S2313 determines the delay from

the WDT Oscillator frequency.

Follow the guidelines from the section “System Clock and Clock Options” in the

ATtiny2313 data sheet to find appropriate clock settings and start-up values.

The crystal Oscillator in AT90S2313 is capable of driving an additional clock buffer from

the XTAL2 output. The ATtiny2313 does not have a rail-to-rail swing on oscillator pins

and can therefore not be used for this purpose. Note however that the new Clock Out

(CKOUT) feature could alternatively be used to drive an additional clock buffer. CKOUT

is located on PD2, which also is used for the External Interrupt 0.

Improvements to

Timer/Counters and

Prescalers

For details about the improved and additional features, please refer to the data sheet.

The following features have been added:

• The Prescalers in ATtiny2313 can be reset.

• Variable top value in PWM mode.

• For Timer/Counter1, Phase and Frequency Correct PWM mode in addition to the

Phase Correct PWM mode.

• Fast PWM mode.

• Timer0 extended with PWM and Output Compare function.

Differences Between

ATtiny2313 and

AT90S2313

Most of the improvements and changes apply to all the Timer/Counters and the descrip-

tion below is written in a general form. A lower case “x” replaces the output channel (x =

A or B), while “n” replaces the Timer/Counter number (n = 0 or 1).

TCNT1 Cleared in PWM Mode In AT90S2313 there are three different PWM resolutions – 8, 9, or 10 bits. Even if only

8, 9, or 10 bits are compared, it is still possible to write values into the TCNT1 Register

that exceed the resolution. Thus, the Timer/Counter has to complete the count to

0xFFFF before the reduced resolution becomes effective (i.e. if 8-bit resolution is

selected and the TCNT1 Register contains 0x0100, the top value (0x00FF) will not be

effective until the counter has counted up to 0xFFFF, turned, and counted down to

0x0000 again). In ATtiny2313 this has been changed so that the unused bits in TCNT1

are being cleared to zero to avoid this unintended counting up to 0xFFFF. In the

ATtiny2313, the TCNT1 Register never exceeds the selected resolution.

OCR1xH Cleared in PWM

Mode

Clearing OCR1xH in PWM mode is slightly different from clearing TCNT1. The

AT90S2313 clears the six most significant bits if 8, 9, or 10 bits PWM mode is selected.

Hence, if 0xFFFF is written to OCR1x in PWM-mode and OCR1x is read back, the result

is 0x03FF regardless of which PWM mode that is selected. In ATtiny2313 the number of

cleared bits depends on the resolution.

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AVR091

Clear Timer/Counter on

Compare Match with

Prescaler

The relation between a Clear on Compare match and the internal counting of the

Timer/Counters has been changed. The Clear on Compare Match in the AT90S2313

clears the Timer/Counter after the first internal count matching the compare value,

whereas the ATtiny2313 clears Timer/Counter after the last internal count matching the

compare value. See Figure 1 and Figure 2 for details on clearing, flag setting, and pin

change. Example: OCR1x = 0x02 when prescaler is enabled (divide clock by 8).

Figure 1. Setting Output Compare Flag/Pin for AT90S2313. “

Indicates where the Output Compare Flag/Pin will be set

Figure 2. Setting Output Compare Flag/Pin for ATtiny2313. “

Indicates where the Output Compare Flag/Pin will be set .

Setting of Output Compare

Pin/Flag with Prescaler

Enabled (Applies to all

Timer/Counters)

The relation between an Output Compare event and the internal counting of the

Timer/Counter has been changed. Output Compare in the AT90S2313 sets the Output

Compare pin/flag after the first internal count matching the compare value, whereas the

ATtiny2313 sets the Output Compare pin/flag after the last internal count matching the

compare value. See Figure 3 and Figure 4 for details on Output Compare Flag setting

and pin change. Example: OCR1x = 0x02, prescaler enabled (divide clock by 8).

Figure 3. Figure 3 Setting Output Compare Flag/Pin for AT90S2313. “

Indicates where the Output Compare Flag/Pin will

be set.

Figure 4. Setting Output Compare Flag/Pin for ATtiny2313. “

Indicates where the Output Compare Flag/Pin will be set.

Write to OCR1x in PWM Mode,

Change to Normal Mode

Before OCR1x is Updated at

the Top, Read OCR1x

As described in the data sheet, the OCR1x Registers are updated at the top value when

written. Thus, when writing the OCR1x in PWM mode, the value is stored in a temporary

buffer. When the Timer/Counter reaches the top, the temporary buffer is transferred to

the actual Output Compare Register. If PWM mode is left after the temporary buffer is

written, but before the actual Output Compare Register is updated, the behavior differs

between ATtiny2313 and AT90S2313.

4298A–AVR–10/03

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