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8-STAGE STATIC SHIFT REGISTERS
HCF4021B
ASYNCHRONOUS PARALLEL IN OR SYNCHRONOUS
SERIAL IN/SERIAL OUT 8 - STAGE STATIC SHIFT REGISTER
n
MEDIUM SPEED OPERATION : 12 MHz
(Typ.) CLOCK RATE AT V DD -V SS = 10V
FULLY STATIC OPERATION
n
n
8 MASTER-SLAVE FLIP-FLOPS PLUS
OUTPUT BUFFERING AND CONTROL
GATING
n
QUIESCENT CURRENT SPECIFIED UP TO
20V
DIP
SOP
n
5V, 10V AND 15V PARAMETRIC RATINGS
n
INPUT LEAKAGE CURRENT
I I = 100nA (MAX) AT V DD = 18V T A =25
ORDER CODES
PACKAGE
°
C
TUBE
T & R
100% TESTED FOR QUIESCENT CURRENT
n
DIP
HCF4021BEY
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B ” STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES”
n
SOP
HCF4021BM1
HCF4021M013TR
DESCRIPTION
The HCF4021B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
This device is an 8-stage parallel or serial input/
serial output register having common CLOCK and
PARALLEL/SERIAL CONTROL inputs, a single
SERIAL data input, and individual parallel ”JAM”
inputs to each register stage. Each register stage
is a D-type, master-slave flip-flop in addition to an
output from stage 8, ”Q” outputs are also available
from stages 6 and 7. Serial entry is synchronous
with the clock but parallel entry is asynchronous.
In this device, entry is controlled by the
PARALLEL/SERIAL CONTROL input. When the
PARALLEL/SERIAL CONTROL input is low, data
is serially shifted into the 8-stage register
synchronously with the positive transition of he
clock line. When the PARALLEL/SERIAL
CONTROL input is high, data is jammed into the
8-stage register via the parallel input lines and
synchronous with the positive transition of the
clock line, the CLOCK input of the internal stage is
”forced” when asynchronous parallel entry is
made. Register expansion using multiple package
is permitted.
PIN CONNECTION
September 2001
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HCF4021B
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
7, 6, 5, 4, 13,
14, 15, 1
PI1 to PI8 Parallel Input
11
SERIAL IN Serial Input
9
PARALLEL/
SERIAL
CONTROL
Parallel/Serial Input Con-
trol
10
CLOCK
Clock Input
2, 3, 12
Q6, Q7, Q8 Buffered Outputs
8
V SS
Negative Supply Voltage
16
V DD
Positive Supply Voltage
TRUTH TABLE
CLOCK
SERIAL INPUT
PARALLEL/
SERIAL
CONTROL
PI - 1
PI - n
Q 1
(INTERNAL)
Q n
X
X
1
0
0
0
0
X
X
1
0
1
0
1
X
X
1
1
0
1
0
X
X
1
1
1
1
1
0
0
X
X
0
Q n -1
1
0
X
X
1
Q n -1
X
X
X
X
Q 1
Q n
X : Don’t Care
LOGIC DIAGRAM
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HCF4021B
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V DD
Supply Voltage
-0.5 to +22
V
V I
DC Input Voltage
-0.5 to V DD + 0.5
V
I I
DC Input Current
±
10
mA
P D
Power Dissipation per Package
200
mW
Power Dissipation per Output Transistor
100
mW
T op
Operating Temperature
-55 to +125
°
C
T stg
Storage Temperature
-65 to +150
°
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V SS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V DD
Supply Voltage
3to20
V
V I
Input Voltage
0 to V DD
V
T op
Operating Temperature
-55 to 125
°
C
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HCF4021B
DC SPECIFICATIONS
Test Condition
Value
Symbol
Parameter
V I
(V)
V O
(V)
|I O |
V DD
(V)
T A =25
°
C
-40 to 85
°
C -55 to 125
°
C
Unit
(
m
A)
Min. Typ. Max. Min. Max. Min. Max.
I L
Quiescent Current 0/5
5
0.04
5
150
150
0/10
10
0.04
10
300
300
m
A
0/15
15
0.04
20
600
600
0/20
20
0.08 100
3000
3000
V OH High Level Output
Voltage
0/5
<1
5
4.95
4.95
4.95
0/10
<1
10 9.95
9.95
9.95
V
0/15
<1
15 14.95
14.95
14.95
V OL
Low Level Output
Voltage
5/0
<1
5
0.05
0.05
0.05
10/0
<1
10
0.05
0.05
0.05
V
15/0
<1
15
0.05
0.05
0.05
V IH
High Level Input
Voltage
0.5/4.5 <1
5
3.5
3.5
3.5
1/9
<1
10
7
7
7
V
1.5/13.5 <1
15
11
11
11
V IL
Low Level Input
Voltage
4.5/0.5 <1
5
1.5
1.5
1.5
9/1
<1
10
3
3
3
V
13.5/1.5 <1
15
4
4
4
I OH
Output Drive
Current
0/5
2.5
<1
5 -1.36 -3.2
-1.1
-1.1
0/5
4.6
<1
5 -0.44
-1
-0.36
-0.36
mA
0/10
9.5
<1
10 -1.1 -2.6
-0.9
-0.9
0/15
13.5
<1
15 -3.0 -6.8
-2.4
-2.4
I OL
Output Sink
Current
0/5
0.4
<1
5
0.44
1
0.36
0.36
0/10
0.5
<1
10
1.1
2.6
0.9
0.9
mA
0/15
1.5
<1
15
3.0
6.8
2.4
2.4
I I
Input Leakage
Current
0/18
Any Input
18
±
10 -5
±
0.1
±
1
±
1
m
A
C I
Input Capacitance
Any Input
5
7.5
pF
The Noise Margin for both ”1” and ”0” level is: 1V min. with V DD =5V, 2V min. with V DD =10V, 2.5V min. with V DD =15V
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HCF4021B
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb =25
°
C, C L = 50pF, R L = 200K
W
, r =t f = 20 ns)
Test Condition
Value (*)
Unit
Symbol
Parameter
V DD (V)
Min. Typ. Max.
CLOCKED OPERATION
t PLH t PHL Propagation Delay Time
5
160 320
10
80
160
ns
15
60
120
t THL t TLH Transition Time
5
100 200
10
50
100
ns
15
40
80
f CL (1) Maximum Clock Input
Frequency
5
3
6
10
6
12
MHz
15
8.5
17
t W
Clock Pulse Width
5
180
90
10
80
40
ns
15
50
25
t r ,t f
Clock Input Rise or Fall
Time
5
15
10
15
m
s
15
15
t setup Setup Time, serial Input
(ref to CL)
5
120
60
10
80
40
ns
15
60
30
t setup Setup Time, Parallel Inputs
(ref to P/S)
5
50
25
10
30
15
ns
15
20
10
t hold
Hold Time, serial in,
parallel in, parallel /serial
control
5
0
10
0
ns
15
0
t WH
P/S Pulse Widht
5
160
80
10
80
40
ns
15
50
25
t rem
P/S Removal Time (ref to
CL)
5
280 140
10
140
70
ns
15
100
50
(*) Typical temperature coefficient for all V DD value is 0.3 %/ ° C.
(1) If more than one unit is cascaded t r CL should be made less than or equal to the sum of the transition time and the fixed propagation delay
of the output of the driving stage of the estimated capacitive load.
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