1934404055 - (2007) Digital Circuit Analysis and Design with Simulink Modeling and Introduction to CPLDs and FPGAs 2nd Ed.pdf

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Digital Circuit Analysis and Design
with Simulink®Modeling
and Introduction to CPLDs and FPGAs
Second Edition
Steven T. Karris
Orchard Publications
www.orchardpublications.com
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Table of Contents
1 Common Number Systems and Conversions
1 − 1
1.1 Decimal, Binary, Octal, and Hexadecimal Systems ..............................................1 − 1
1.2 Binary, Octal, and Hexadecimal to Decimal Conversions ....................................1 − 3
1.3 Decimal to Binary, Octal, and Hexadecimal Conversions ....................................1 − 3
1.4 Binary − Octal − Hexadecimal Conversions ..............................................................1 − 7
1.5 Summary ................................................................................................................1 − 9
1.6 Exercises ...............................................................................................................1 − 11
1.7 Solutions to End − of − Chapter Exercises ...............................................................1 − 12
2 Operations in Binary, Octal, and Hexadecimal Systems
2 − 1
2.1 Binary System Operations 2 − 1
2.2 Octal System Operations 2 − 2
2.3 Hexadecimal System Operations 2 − 5
2.4 Complements of Numbers ....................................................................................2 − 6
2.4.1 Tens − Complement ......................................................................................2 − 7
2.4.2 Nines − Complement ....................................................................................2 − 7
2.4.3 Twos − Complement .....................................................................................2 − 8
2.4.4 Ones − Complement .....................................................................................2 − 9
2.5 Subtraction with Tens − and Twos − Complements .............................................2 − 10
2.6 Subtraction with Nines − and Ones − Complements ............................................2 − 11
2.7 Summary .............................................................................................................2 − 14
2.8 Exercises .............................................................................................................2 − 16
2.9 Solutions to End − of − Chapter Exercises .............................................................2 − 18
MATLAB Computations: Pages 2 − 4, 2 − 6, 2 − 19 through 2 − 21, 2 − 23
3 Sign Magnitude and Floating Point Arithmetic
3 − 1
3.1 Signed Magnitude of Binary Numbers .................................................................3 − 1
3.2 Floating Point Arithmetic ....................................................................................3 − 2
3.2.1 The IEEE Single Precision Floating Point Arithmetic ...............................3 − 3
3.2.2 The IEEE Double Precision Floating Point Arithmetic .............................3 − 7
3.3 Summary ...............................................................................................................3 − 9
3.4 Exercises .............................................................................................................3 − 10
3.5 Solutions to End − of − Chapter Exercises .............................................................3 − 11
MATLAB Computations: Pages 3 − 1 through 3 − 2, 3 − 11
Digital Circuit Analysis and Design with Simulink ® Modeling
i
and Introduction to CPLDs and FPGAs, Second Edition
Copyright © Orchard Publications
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4 Binary Codes
4 − 1
4.1 Encoding ................................................................................................................ 4 − 1
4.1.1 Binary Coded Decimal (BCD) .................................................................... 4 − 1
4.1.2 The Excess − 3 Code ..................................................................................... 4 − 2
4.1.3 The 2*421 Code .......................................................................................... 4 − 3
4.1.4 The Gray Code ............................................................................................ 4 − 4
4.2 The American Standard Code for Information Interchange (ASCII) Code ........ 4 − 5
4.3 The Extended Binary Coded Decimal Interchange Code (EBCDIC) .................. 4 − 8
4.4 Parity Bits .............................................................................................................. 4 − 8
4.5 Error Detecting and Correcting Codes ................................................................. 4 − 9
4.6 Cyclic Codes .......................................................................................................... 4 − 9
4.7 Summary .............................................................................................................. 4 − 14
4.8 Exercises .............................................................................................................. 4 − 16
4.9 Solutions to End − of − Chapter Exercises .............................................................. 4 − 17
5 Fundamentals of Boolean Algebra
5 − 1
5.1 Basic Logic Operations .......................................................................................... 5 − 1
5.2 Fundamentals of Boolean Algebra ........................................................................ 5 − 1
5.2.1 Postulates ..................................................................................................... 5 − 1
5.2.2 Theorems ..................................................................................................... 5 − 2
5.3. Truth Tables 5 − 3
5.4 Summary ................................................................................................................ 5 − 5
5.5 Exercises ................................................................................................................ 5 − 7
5.6 Solutions to End − of − Chapter Exercises ................................................................ 5 − 8
6 Minterms and Maxterms
6 − 1
6.1 Minterms .................................................................................................................6 − 1
6.2 Maxterms ................................................................................................................6 − 2
6.3 Conversion from One Standard Form to Another .................................................6 − 3
6.4 Properties of Minterms and Maxterms ...................................................................6 − 4
6.5 Summary .................................................................................................................6 − 9
6.6 Exercises ................................................................................................................6 − 10
6.7 Solutions to End − of − Chapter Exercises ...............................................................6 − 12
7 Combinational Logic Circuits
7 − 1
7.1 Implementation of Logic Diagrams from Boolean Expressions ..............................7 − 1
7.2 Obtaining Boolean Expressions from Logic Diagrams ........................................ 7 − 10
7.3 Input and Output Waveforms ............................................................................. 7 − 11
7.4 Karnaugh Maps .................................................................................................... 7 − 13
ii
Digital Circuit Analysis and Design with Simulink ® Modeling
and Introduction to CPLDs and FPGAs, Second Edition
Copyright © Orchard Publications
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7.4.1 K − map of Two Variables ............................................................................7 − 14
7.4.2 K − map of Three Variables .........................................................................7 − 15
7.4.3 K − map of Four Variables ............................................................................7 − 15
7.4.4 General Procedures for Using a K − map of n Squares ................................7 − 17
7.4.5 Don’t Care Conditions ...............................................................................7 − 20
7.5 Design of Common Logic Circuits ........................................................................7 − 21
7.5.1 Parity Generators/Checkers .......................................................................7 − 22
7.5.2 Digital Encoders .........................................................................................7 − 27
7.5.3 Decimal − to − BCD Encoder .........................................................................7 − 31
7.5.4 Digital Decoders .........................................................................................7 − 37
7.5.5 Equality Comparators .................................................................................7 − 40
7.5.6 Multiplexers and Demultiplexers ...............................................................7 − 44
7.5.7 Arithmetic Adder and Subtractor Logic Circuits ......................................7 − 52
7.6 Summary ...............................................................................................................7 − 63
7.7 Exercises ................................................................................................................7 − 65
7.8 Solutions to End − of − Chapter Exercises ...............................................................7 − 68
Simulink Modeling: Pages 7 − 3, 7 − 12, 7 − 25, 7 − 29 through 7 − 30, 7 − 47, 7 − 50,
7 − 56 through 7 − 60
8 Sequential Logic Circuits
8 − 1
8.1 Introduction to Sequential Circuits ........................................................................ 8 − 1
8.2 Set − Reset (SR) Flip Flop ........................................................................................8 − 1
8.3 Data (D) Flip Flop ..................................................................................................8 − 4
8.4 JK Flip Flop .............................................................................................................8 − 5
8.5 Toggle (T) Flip Flop ................................................................................................8 − 6
8.6 Flip Flop Triggering .................................................................................................8 − 7
8.7 Edge − Triggered Flip Flops ......................................................................................8 − 8
8.8 Master / Slave Flip Flops .........................................................................................8 − 8
8.9 Conversion from One Type of Flip Flop to Another ............................................8 − 11
8.10 Analysis of Synchronous Sequential Circuits .......................................................8 − 13
8.11 Design of Synchronous Counters .........................................................................8 − 23
8.12 Registers ................................................................................................................8 − 28
8.13 Ring Counters .......................................................................................................8 − 34
8.14 Ring Oscillators .....................................................................................................8 − 37
8.15 Summary ...............................................................................................................8 − 39
8.16 Exercises ................................................................................................................8 − 42
8.17 Solutions to End − of − Chapter Exercises ...............................................................8 − 45
Simulink Modeling: Pages 8 − 19, 8 − 37
Digital Circuit Analysis and Design with Simulink ® Modeling
iii
and Introduction to CPLDs and FPGAs, Second Edition
Copyright © Orchard Publications
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9 Memory Devices
9 − 1
9.1 Random − Access Memory (RAM) ......................................................................... 9 − 1
9.2 Read − Only Memory (ROM) ..................................................................................9 − 3
9.3 Programmable Read − Only Memory (PROM) .......................................................9 − 7
9.4 Erasable Programmable Read − Only Memory (EPROM) ......................................9 − 9
9.5 Electrically − Erasable Programmable Read − Only Memory (EEPROM) ..............9 − 10
9.6 Flash Memory .......................................................................................................9 − 10
9.7 Memory Sticks ......................................................................................................9 − 10
9.8 Cache Memory .....................................................................................................9 − 11
9.9 Virtual Memory ....................................................................................................9 − 11
9.10 Scratch Pad Memory ............................................................................................9 − 12
9.11 The Simulink Memory Block ...............................................................................9 − 12
9.12 Summary ..............................................................................................................9 − 14
9.13 Exercises ...............................................................................................................9 − 16
9.14 Solutions to End − of − Chapter Exercises ...............................................................9 − 17
Simulink Modeling: Pages 9 − 6, 9 − 12
10 Advanced Arithmetic and Logic Operations
10 − 1
10.1 Computers Defined .............................................................................................10 − 1
10.2 Basic Digital Computer System Organization and Operation ............................10 − 2
10.3 Parallel Adder .....................................................................................................10 − 4
10.4 Serial Adder ........................................................................................................10 − 5
10.5 Overflow Conditions ...........................................................................................10 − 6
10.6 High - Speed Addition and Subtraction ...............................................................10 − 9
10.7 Binary Multiplication ........................................................................................10 − 10
10.8 Binary Division ..................................................................................................10 − 13
10.9 Logic Operations of the ALU ...........................................................................10 − 14
10.10 Other ALU functions ........................................................................................10 − 15
10.11 Logic and Bit Operations with Simulink Blocks ...............................................10 − 16
10.11.1 The Logical Operator Block ..............................................................10 − 16
10.11.2 The Relational Operator Block .........................................................10 − 16
10.11.3 The Interval Test Block .....................................................................10 − 17
10.11.4 The Interval Test Dynamic Block .....................................................10 − 18
10.11.5 The Combinatorial Logic Block ........................................................10 − 19
10.11.6 The Compare to Zero Block ..............................................................10 − 24
10.11.7 The Compare to Constant Block ......................................................10 − 25
10.11.8 The Bit Set Block ..............................................................................10 − 26
10.11.9 The Clear Bit Block ...........................................................................10 − 27
10.11.10 The Bitwise Operator Block ..............................................................10 − 28
iv
Digital Circuit Analysis and Design with Simulink ® Modeling
and Introduction to CPLDs and FPGAs, Second Edition
Copyright © Orchard Publications
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