3.13 design ideas.pdf

design ideas

readerS SOLVe deSIGN PrOBLeMS

Circuit maximizes pulse-width-

modulated DAC throughput

Ajoy Raman, Bangalore, India

DIs Inside

52 A circuit for mains syn-

chronization has two separate

outputs for each half-period

55 Low-component-count

zero-crossing detector is

low power

57 DC-DC converter starts up

and operates from a single

photocell

58 Filter quashes 60-Hz

interference

▶ To see and comment on

all of EDN ’s Design Ideas, visit

www.edn.com/designideas.

↘ Simple DACs realized by low-

ate the capture signals OC 1 and OC 4 .

Clock/4 is fed to an internal 16-bit timer

whose period is set for a count of 1200

corresponding to a PWM frequency of 20

kHz. Signal OC 4 is mostly high and goes

low at a fixed count of 1170 as a reference

for ramp generation. IC 1A , along with

Q 1 , forms a precision constant-current

source that linearly charges capacitor C 2

when Q 2 is off. This signal inverted by

IC 3A switches Q 2 on for a period of 30

counts to discharge C 2 for the start of the

next ramp. IC 1B buffers, amplifies, and

offsets the ramp; potentiometers R 2 and

R 5 adjust the offset and gain.

The OC 1 falling edge controls the

PWM DAC sample timing relative to

pass filtering microcontroller-

generated pulse-width-modulated

(PWM) signals have a response that is

typically a tenth of the PWM frequen-

cy. This Design Idea is a novel imple-

mentation of a previously published

method 1 employing a reference ramp

whose output is sampled and held by

the PWM signal. This approach results

in a throughput rate equal to the PWM

frequency.

You can use the circuit in Figure 1 to

implement a ±10V 10-bit DAC with a

throughput of 20 kHz. A DSPIC30F4011

microcontroller (not shown) is operated

at a clock frequency of 96 MHz to gener-

the ramp voltage. The data word to be

converted determines the OC 1 duty

cycle by comparing it internally in the

15V

R 3

18k

R 1

2.7k

R 2

R 4

56k

–15V

R 6

15V

IC 1A

LF353

Q 1

R 5

10k

IC 1B

LF353

ANALOG IN

BC177

IC 2

LF398

DAC

OUTPUT

R 7

18k

15V

C 2

0.1 F

MYLAR

C 1

1800 pF

PIN 19

OC 4

S/H IN

Q 2

R 8

2.2k

IC 3A

CD40106

BC107

–15V

OUTPUTS

FROM

DSPIC30F4011

R 9

1.8k

IC 3B

CD40106

C 3

680 pF

PIN 23

OC 1

Figure 1 The off-page microcontroller gene rate s signals for ramp control (OC 4 ) and sam ple t iming (OC 1 ).

[ www.edn.com ]

March 2013 | EDN 51

design ideas

the initial nonlinear region of the ramp

so that the PWM DAC shows good

linearity with a LSB of 20 mV and an

accuracy of ±40 mV. Additional PWM

DACs could also be implemented using

capture PWM outputs OC 2 and OC 3 .

Figure 2 shows the waveforms to

be expected for a DAC output corre-

sponding to 256 on a 10-bit scale of

1024. OC 4 forms the PWM reference

based on which a 20-kHz bipolar ramp

signal is output at Pin 7 of IC 1B . This

ramp is sampled and held at a count of

256+88=344, corresponding to a DAC

output of −5 V. EDN

IC 1B - PIN 7 RAMP

ANALOG

SIGNALS

DAC OUTPUT

–10

S/H SIGNAL FOR 344 COUNTS

OC 1 PWM

DAC SIGNAL

DIGITAL

SIGNALS

OC 4 PWM REF

100

TIME ( SEC)

Figure 2 The differentiated OC 1 falling edge generates the S/H sample pulse at the

ramp − 5V point.

RefeRences

1 Kester, Walt (editor), The Data

Conversion Handbook , section 3-1,

pg 3-28, Newnes, 2005, http://bit.ly/

KjU8fU.

2 Raman, Ajoy, “Universal Analog

Hardware Testbench,” http://bit.ly/

QCYXmb.

microcontroller with the internal 16-bit

timer. C 3 and R 9 differentiate the result-

ing PWM signal; IC 3B then inverts it,

forming a 1-μsec sample signal for the

sample-and-hold IC 2 . Pin 5 of IC 2 forms

the DAC output and is adjusted to −10,

0, and +10V for OC 1 PWM counts of

88, 600, and 1112, respectively, cor-

responding to a 10-bit count of 1024.

The count offset of 88 helps to avoid

ing cancels them out. If you average

several consecutive pairs of measure-

ments, the results will improve still fur-

ther. Instead of counting the half-peri-

ods of the mains, you may find that a

circuit having two outputs for synchro-

nization with odd or even half-periods

of the mains can come in handy.

The circuit shown in Figure 1 pro-

vides two separate and optically isolated

outputs, ISO 1 and ISO 2 , for synchroni-

zation with the desired half-period of

the mains. Figure 2 shows the results

of simulation (using the free version of

A circuit for mains synchronization

has two separate outputs

for each half-period

Dušan Ponikvar, University of Ljubljana, Ljubljana, Slovenia

↘ Often a measurement of weak

consecutive measurements separated in

time by an odd number of half-periods

of the mains and calculating the average

of the two measurements. The interfer-

ing signals have opposite polarities in

consecutive measurements, and averag-

signals has to be performed in the

presence of strong interference from the

ac power mains. If the interfering signal

cannot be filtered out, then you can still

obtain a clean result by making two

R 6

10k

R 7

10k

D 1

R 1A

120k

R 1B

120k

D 2

C 3

1 F

10V

ISO 1

R 3

47k

OC 1

4N33

D 5

C 1

10 nF

MAINS

R 2A

120k

R 2B

120k

Q 5

D 3

OC 2

4N33

C 2

1 F

10V

R 4

47k

2N3904

ISO 2

D 4

Figure 1 Mains zero crossings are marked by the optically isolated outputs.

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52 EDN | March 2013

design ideas

ac, and the reverse voltage on the diodes is

less than 6V. The peak current through the

optocoupler LEDs is below 8 mA. The only

components that are exposed to the mains

are input resistors R 1A , R 1B , R 2B , and R 2B . They

have equal values, so each one needs to with-

stand 25% of the mains voltage.

The measurements obtained from the con-

structed circuit show good correlation with

the simulation results. Figure 3 shows output

signals; Figure 4 shows the timing detail of the

zero crossing and corresponding output pulse

for three different values of C 1 . EDN

ISO 1

ISO 2

VOLTAGE (V)

MAINS

RefeRences

1 “DIY: Isolated high-quality mains voltage

zero-crossing detector,” www.dextrel.net/

diyzerocrosser.htm.

2 Matteini, Luca, “Mains-driven zero-crossing

detector uses only a few high-voltage parts,”

EDN , Dec 1, 2011, www.edn.com/4368740.

TIME (mSEC)

Figure 2 Simulation results demonstrate the circuit action.

TINA-TI). The circuit accepts mains input from 80V ac to

240V ac, and consumes less than a milliamp of current.

The duration of the pulses at outputs ISO 1 and ISO 2 is

less than a millisecond, and capacitor C 1 can be adjusted to

achieve the exact alignment of the falling edges of outputs

ISO 1 and ISO 2 with the zero crossing of the mains. All diodes,

D 1 to D 5 , are small-signal type 1N4148 or similar.

The circuit works as follows: During the positive half-

period of the mains, C 3 is charged through R 1A , R 1B , D 1 and D 5 ,

D 3 , R 2B , and R 2A . The effective time constant, τ, for charging

is about 43 msec, and C 3 barely picks up some charge in the

half-period. Once the mains drops below the voltage stored

on C 3 (this happens just before the end of the half-period),

Figure 3 Measured output signals ISO 1 and ISO 2 and the

mains voltage verify the circuit operation.

The cIrcuIT accePTS MaINS

INPuT frOM 80V ac TO 240V ac.

the charging stops and current begins to flow from C 3 through

R 3 into the base of Q 5 , turning it on. This discharges C 3

through the LED in optocoupler OC 1 , and produces a pulse

at the output ISO 1 of the circuit. During the negative half-

period, the action repeats, only this time D 4 and D 2 are used

to charge C 2 , and R 4 is used to activate Q 5 when the negative

half-period is nearly finished.

The duration of the output pulse can be shortened to

about 600 μsec by increasing the time constant—therefore

by increasing the value of resistors R 1 and R 2 or capacitors

C 2 and C 3 —but this also reduces the range of acceptable

input voltages.

The detailed simulation reveals that the maximum voltage

on C 2 and C 3 is less than 5V, with 250V ac connected to the

input; a voltage rating of 10V for the capacitors is sufficient.

Additionally, the maximum voltage on C 1 is less than 10V

Figure 4 C 1 determines the position of the pulse leading edge

in this detail from the center portion of Figure 3. The horizon-

tal scale is 200 µsec/div. Pulses are vertically shifted for bet-

ter visibility: C 1 = 0 (upper), 12 nF (middle), and 22 nF (lower).

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54 EDN | March 2013

Low-component-count zero-crossing

detector is low power

C Castro-Miguens and M Pérez Suárez, University of Vigo, Spain,

and JB Castro-Miguens, Cesinel, Madrid, Spain

↘ There are many circuits pub-

lished showing zero-crossing

detectors for use with 50- and

60-Hz power lines. Though the cir-

cuit variations are plentiful, many

have shortcomings. This Design

Idea shows a circuit that uses only

a few commonly available parts and

provides good performance with

low power consumption.

In the circuit shown in Figure

1 , a waveform is produced at V O

with rising edges that are synchro-

nized with the zero crossings of the

line voltage, V AC . The circuit can

be easily modified so that it pro-

duces a falling-edge waveform that

is synchronized with V AC .

The circuit operates as follows.

At the zero crossings of V AC , the current through the capaci-

tor and the LED of the HCPL-4701 optocoupler satisfies

Equation 1 below. Equation 2 shows the standard conver-

sion between radians per second and hertz; it also shows

the derivation and explanation for v i (t). Equations 3 and

4 show the simplification used in Equation 1 . Because the

voltage across the LED is close to constant, differentiation

of that value with respect to time results in a zero value.

HCPL-4701

I C (t)

V C =5V

100 nF

1N4007

R 1

0.25W

V I (t)

V AC

1,4,7: N.C.

V O

D 1

1N4007

3.3k

–

Figure 1 The zero-crossing detector uses few components and consumes very little

power. The V O signal has a rising edge that is coincident with each zero crossing of the

line voltage, V AC .

given minimum supply-voltage value, the intensity exceeds

the triggering threshold value for the optocoupler. In the case

of the HCPL-4701, it is I F(ON) =40 μA.

Diode D 1 not only allows for the capacitor to discharge

but also prevents the application of a reverse voltage on the

LED. The maximum reverse input voltage of the HCPL-

4701 is 2.5V.

Resistor R 1 is included in order to discharge the energy

stored in the capacitor in the latter portion of each cycle of

v i (t) when i c (t)<0 ( Figure 1 ). Its maximum value is limited

by the capacitor, by the peak value of the supply voltage

(V AC-PEAK ), and by the maximum acceptable time delay of

the current rising edges through the LED with respect to

the corresponding ac-voltage zero crossing ( Figure 2 ). Its

minimum value is limited by the maximum allowable power

dissipation in R 1 ([V AC-RMS ] 2 /R 1 ). A practical compromise has

to be reached.

Table 1 shows the time delay (t DELAY ) of the current rising

edges through the LED and the power dissipation for three

different values of R 1 . Notice that the time delay of the ris-

ing edges of V O with respect to the zero crossings of V AC must

[v i (t)–v LED ] C

i c (t)=i LED (t)=C

v i (t)

=C V AC–PK ×cos( t) i c (0) C× ×V AC–PK

××

(1)

where =2× ×f AC and

v i (t) =|V AC (t)|=|V AC–PK ×sin( t)|.

(2)

[v i (t)–v LED ]

v i (t)

–C

v LED C

v i (t),

(3)

TABLe 1 i LED timE DELay for DiffErEnt

vaLuEs of r 1

R 1

dt ×v LED 0 (v LED constant).

because C

(4)

t DELAY (μSeC)

V 2 AC-RMS /R 1 (mW)

470 k Ω

112.5

The peak value of the current through the LED is a func-

tion of the capacitor, C, so you must choose a value for C

under the constraint that at the initial time (t=0) and for a

820 k Ω

100

64.5

4.7 M Ω

450

11.2

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March 2013 | EDN 55

design ideas

350

300

250

200

150

100

R 1 =820k

R 1 =4.7M

V AC-PEAK =325V

v i (t)

t DELAY

(R 1 =4.7M)

t DELAY

(R 1 =820k)

6e-005

4e-005

I LED(t)

2e-005

–2e-005

0.004

0.006

0.008

0.01

0.012

TIME (SEC)

EDNDI5314 Fig 2.eps DIANE

Figure 2 The relationship between v i (t) and I LeD (t) is a function of

the value of R 1 . The time delay between the zero crossing and the

LeD current is shown.

Figure 3 empirical results are shown for V AC = 230V RMS , C = 0.5 nF,

and R 1 = 560 k Ω .

Figure 4 empirical results are shown for V AC = 115V RMS , C = 1 nF,

and R 1 = 220 k Ω .

Figure 5 empirical results are shown for V AC = 267V RMS , C = 1 nF,

and R 1 = 220 k Ω .

include an additional delay for the optocoupler’s propaga-

tion time delay. The HCPL-4701 has a typical propagation

time delay of 70 μsec.

Based on the previous information, the following practi-

cal values for C and R 1 are obtained:

• For V AC =230V RMS ±20% ( Figure 3 ): C=0.5 nF/400V

(MKT-HQ 370 polyester metallized, MKT series), R 1 =560

kΩ/0.25W, t DELAY =114 μsec (the time delay in the rising

edges of V O with respect to the zero crossings of V AC ), and

P≈100 mW (average power from the ac line).

• For V AC =115V RMS ±20% ( Figure 4 ): C=1 nF/200V,

R 1 =220 kΩ/0.25W, t DELAY =130 µsec (time delay in the rising

edges of V O with respect to the zero crossings of V AC ), and

P≈65 mW (average power from the ac line).

• For operation from 80 to 280V RMS : C=1 nF/400V and

R 1 =330 kΩ/0.25W.

Empirical results are shown for V AC =267V RMS , C 1 =1 nF,

and R 1 =220 kΩ ( Figure 5 ). Additional empirical results can

be viewed in the online version of this Design Idea, which

is available at www.edn.com/4408530.

Note that as with any device connected directly to the

mains, exercise extreme caution while bench testing the

circuit. Follow proper guidelines when laying out a printed

circuit board. EDN

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56 EDN | March 2013

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