w65c51n.pdf

March 30, 2010

W65C51N

Asynchronous Communications

Interface Adapter (ACIA)

WDC reserves the right to make changes at any time without notice in order to improve

design and supply the best possible product. Information contained herein is provided

gratuitously and without liability, to any user. Reasonable efforts have been made to

verify the accuracy of the information but no guarantee whatsoever is given as to the

accuracy or as to its applicability to particular uses. In every instance, it must be the

responsibility of the user to determine the suitability of the products for each application.

WDC products are not authorized for use as critical components in life support devices

or systems. Nothing contained herein shall be construed as a recommendation to use

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Policies, copies of which are available upon request.

including the right of reproduction, in whole, or in part, in any form.

INTRODUCTION

The WDC CMOS W65C51N Asynchronous Communications Interface Adapter (ACIA) provides an easily

implemented, program controlled interface between 8-bit microprocessor based systems and serial

communication data sets and modems.

The ACIA has an internal baud rate generator. This feature eliminates the need for multiple component

support circuits, a crystal being the only other part required. The Transmitter baud rate can be selected

under program control to be either 1 of 15 different rates from 50 to 19,200 baud, or at 1/16 times an

external clock rate. The Receiver baud rate may be selected under program control to be either the

Transmitter rate or at 1/16 times the external clock rate. The ACIA has programmable word lengths of 5,

6, 7 or 8 bits; even, odd or no parity (Mark Parity only for Transmitter); 1, 1½ or 2 bit stops.

The ACIA is designed for maximum-programmed control from the microprocessor (MPU) to simplify

hardware implementation. Three separate registers permit the MPU to easily select the W65C51N

operating modes and data checking parameters and determine operational status.

The Command Register controls parity, receiver echo mode, transmitter interrupt control, the state of the

RTSB line, receiver interrupt control and the state of the DTRB line.

The Control Register controls the number of stop bits, word length, receiver clock source and baud rate.

The Status Register indicates the states of the IRQB, DSRB, and DCDB lines, Transmitter and Receiver

Data Registers and Overrun, Framing and Parity Error conditions.

The Transmitter and Receiver Data Registers are used for temporary data storage by the ACIA Transmit

and Receive circuits.

FEATURES

 Low power CMOS N-well silicon gate technology

 Replacement for CMD / GTE / Harris / MOS Technology / GE / RCA / Synertek / Motorola /

Rockwell R6551, G65SC51, 65C51, 6551, CPD65C51, 6850

 Full duplex operation with buffered receiver and transmitter

 Data set/modem control functions

 Internal baud rate generator with 15 programmable baud rates (50 to 19,200)

 Program-selectable internally or externally controlled receiver rate

 Programmable word lengths, number of stop bits and parity bit generation and detection

 Programmable interrupt control

 Program reset

 Program-selectable serial echo mode

 Two chip selects

 5.0 VDC ± 5% supply requirements

 28 pin plastic DIP package

 32 pin LQFP package

 Full TTL compatibility

 Compatible with 65xx and 68xx microprocessors

VSS

CS0

CS1B

RESB

RxC

XTLI

XLT0

RTSB

CTSB

TxD

DTRB

RxD

RS0

RS1

RWB

PHI2

IRQB

DSRB

DCDB

VDD

RxC

XTLI

XTL0

RTSB

CTSB

TxD

DTRB

W65C51N

Figure 1a 28 Pin PDIP Pin Out Figure 1b 32 Pin LQFP Pin Out

TRANSMIT

CONTROL

CTSB

D0-D7

DATA BUS

BUFFER

TRANSMITER

DATA

TRANSMIT

SHIFT

TxD

IRQB

INTERRUPT

LOGIC

STATUS

DCDB

DSRB

RxC

XTLI

XTLO

DTRB

RTSB

RWB

CS0

CS1B

CONTROL

BAUD RATE

GENERATOR

I/O

CONTROL

COMMAND

RS0

RS1

PHI2

TIMING &

CONTROL

RECEIVER

DATA

RECEIVE

SHIFT

RxD

RESB

RECEIVE

CONTROL

Figure 2 ACIA Internal Organization

FUNCTIONAL DESCRIPTION

A block diagram of the ACIA is presented in Figure 3 followed by a description of each functional element

of the device.

DATA BUS BUFFERS

The Data Bus Buffer interfaces the system data lines to the internal data bus. The Data Bus Buffer is bi-

directional. When the RWB line is high and the chip is selected, the Data Bus Buffer passes the data

from the system data lines to the ACIA internal data bus. When the RWB line is low and the chip is

selected, the Data Bus Buffer writes the data from the internal data bus to the system data bus.

INTERRUPT LOGIC

The Interrupt Logic will cause the IRQB line to the microprocessor to go low when conditions are met that

require the attention of the microprocessor. The conditions which can cause an interrupt will set bit 7 and

the appropriate bit of bits 3 through 6 in the Status Register, if enabled. Bits 5 and 6 correspond to the

Data Carrier Detect (DCDB) logic and the Data Set Ready (DSRB) logic. Bits 3 and 4 correspond to the

Receiver Data Register full and the Transmitter Data Register empty conditions. These conditions can

cause an interrupt request if enabled by the Command Register.

I/O CONTROL

The I/O Control Logic controls the selection of internal registers in preparation for a data transfer on the

internal data bus and the direction of the transfer to or from the register. The registers are selected by the

TIMING AND CONTROL

The Timing and Control logic controls the timing of data transfers on the internal data bus and the

registers, the Data Bus Buffer and the microprocessor data bus and hardware reset features.

Timing is controlled by the system PHI2 clock input. The chip will perform data transfers to or from the

microcomputer data bus during the PHI2 high period when selected.

The Timing and Control Logic will initialize all registers when the Reset (RESB) line goes low. See the

individual register description for the state of the registers following a hardware reset.

TRANSMITTER AND RECEIVER DATA REGISTERS

These registers are used as temporary data storage for the ACIA Transmit and Receive Circuits. Both

the Transmitter and Receiver are selected by a Register Select 0 (RS0) and Register Select 1 (RS1) low

condition. The Read/Write (RWB) line determines which actually uses the internal data bus; the

Transmitter Data Register is write only and the Receiver Data Register is read only.

Bit 0 is the first bit to be transmitted from the Transmitter Data Register (least significant bit first). The

higher order bits follow in order. Unused bits in this register are “don’t care”.

The Receiver Data Register holds the first received data bit in bit 0 (least significant bit first). Unused

high-order bits are “0”. Parity bits are not contained in the Receiver Data Register. They are stripped off

after being used for parity checking.

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