cache.pdf

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Cache Designs and Tricks
Craig C. Douglas
University of Kentucky Computer Science Department
Lexington, Kentucky, USA
Yale University Computer Science Department
New Haven, Connecticut, USA
douglas@ccs.uky.edu or douglas-craig@cs.yale.edu
http://www.ccs.uky.edu/~douglas
http://www.mgnet.org
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Cache Methodology
Motivation:
1. Time to run code = clock cycles running code +
clock cycles waiting for memory
2. For many years, CPU’s have sped up an average of 72% per year
over memory chip speeds.
Hence, memory access is the bottleneck to computing fast.
Definition of a cache:
1. Dictionary: a safe place to hide or store things.
2. Computer: a level in a memory hierarchy.
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Diagrams
Serial:
CPU
Registers
Logic Cache
Main Memory
Parallel:
Shared Memory
. . .
Network
Cache 1
Cache 2
. . .
Cache p
. . .
CPU 1
CPU 2
CPU p
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Tuning for Caches
1. Preserve locality.
2. Reduce cache thrashing.
3. Loop blocking when out of cache.
4. Software pipelining.
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Memory Banking
This started in the 1960’s with both 2 an d 4 way interleaved memory
banks. Each bank can produce one unit of memory per bank cycle.
Multiple reads and writes are possible in parallel.
The bank cycle time is currently 4-8 times the CPU clock time and getting
worse every year.
Very fast memory (e.g., SRAM) is unaffordable in large quantities.
This is not perfect. Consider a 2 way interleaved memory and a stride 2
algorithm. This is equivalent to non-interleaved memory systems.
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