Deep Submicron CMOS Circuit Design Simulator In Hands.pdf

(14738 KB) Pobierz
Microsoft Word - Book ch0q.doc
D EEP SUBMICRON CMOS DESIGN
Contents
Deep-submicron
CMOS circuit design
Simulator in hands
Etienne Sicard
Sonia Delmas Bendhia
Version December 2003
This book is under consideration for publication by
Brooks/Cole Publishing Company
3450 South 3650 East Street
Salt Lake City, Utah 84109, USA
www.brookscole.com
(Contact: Bill.Stenquist@wadsworth.com)
1
20/12/03
D EEP SUBMICRON CMOS DESIGN
Contents
Acknowledgements
We would like our early colleagues Jean-Francois Habigand, Kozo Kinoshita, Antonio Rubio for their support
throughout the development of the Microwind, Dsch tools. The project of writing a book that seemed initially to be
shadowy took form and substance, and led to this present work. We would like to thank Joseph-Georges Ferrante for
having faith in our ability to drive ambitious microelectronics research projects, and having provided us a continuous
support over the last ten years. Productive technical discussions with Jean-Pierre Schoellkopf, Amaury Soubeyran,
Thomas Steinecke, Gert Voland and Jean-Louis Noullet are also gratefully acknowledged.
Special thanks are due to technical contributors to the Dsch and Microwind software (Chen Xi, Jianwen Huang), to our
colleagues at INSA how always supported this work, to numerous professors, students and engineers who patiently
debugged the technical contents of the book and the software, and gave valuable comments and suggestions. Also, we
would like to thank Marie-Agnes Detourbe for having carefully reviewed the manuscript.
Finally we would like to acknowledge our biggest debt to our parents and to our companion for their constant support.
About the authors
etienne.sicard@insa-tlse.fr
ETIENNE SICARD was born in Paris, France, in June 1961. He received a B.S degree in 1984 and a PhD in Electrical
Engineering in 1987 both from the University of Toulouse. He was granted a scholarship from the Japanese Ministry of
Education and stayed 18 months at the University of Osaka, Japan. Previously a professor of electronics in the
department of physics, at the University of Balearic Islands, Spain, E. Sicard is currently professor at the INSA
Electronic Engineering School of Toulouse. His research interests include several aspects of integrated circuit design
including crosstalk fault tolerance, and electromagnetic compatibility of integrated circuits. Etienne is the author of
several educational software in the field of microelectronics and sound processing.
sonia.bendhia@insa-tlse.fr
2
20/12/03
23255736.001.png 23255736.002.png
D EEP SUBMICRON CMOS DESIGN
Contents
Sonia DELMAS BENDHIA was born in Toulouse, April 1972, She received an engineering diploma in 1995, and the
Ph.D. in Electronic Design from the National Institute of Applied Sciences, Toulouse, France, in 1998. Sonia Bendhia
is currently a senior lecturer in the INSA of Toulouse, Department of Electrical and Computer Engineering. Her
research interests include signal integrity in deep sub-micron CMOS Ics, analog design and electromagnetic
compatibility of systems . Sonia is the author of technical papers concerning signal integrity and EMC.
About Microwind and Dsch
The present book introduces the design and simulation of CMOS integrated circuits, and makes an extensive use of PC
tools Microwind2 and Dsch2. These tools are freeware.
The web link is http://www.microwind.org
In memory…
In memory of John Uyemura
3
20/12/03
D EEP SUBMICRON CMOS DESIGN
Contents
Contents
Chapter
Page
1
Introduction
Technology scale down
Frequency Improvement
Increased layers
Reduced power supply
2
The MOS device
The MOS Logic simulation of the MOS
MOS layout
Vertical aspect of the MOS
Static MOS characteristics
Dynamic MOS behavior
Analog simulation
Mos options
Transmission gate: the perfect switch
Layout considerations
3
MOS modeling
The MOS model 1
The MOS model 3
The model BSIM4
Temperature effects on the MOS
High frequency behavior of the MOS
4
The Inverter
The logic Inverter
The CMOS inverter (Power, supply, frequency)
Layout design (plasma, latchup)
Simulation of the inverter
Views of the process
Buffer
3-state inverter
Analog behavior of the inverter
Ring oscillator
Temperature effects
4
20/12/03
D EEP SUBMICRON CMOS DESIGN
Contents
5
Interconnects
Signal propagation
Capacitance load
Resistance effect
Inductance effect
Buffers
Clock tree
Supply routing
6
Basic Gates
Introduction
From boolean expression to layout
NAND gate (micron, sub-micron)
OR3 gate
XOR
Complex gates
Multiplexors (Mux-demux)
Pulse generator
7
Arithmetics
Data formats: unsigned, signed fixed
Half adder gate
Full adder gate
4-bit adder
Comparator
Multiplier
ALU
Low power arithmetics
8
Latches
RS latch
D-Latch
Edge-trigged latch
Latch optimization (conso, speed, fanout)
Counter
Project: programmable pulse generator
9
FPGA
Goals
Mux for FPGA
Configurable logic block
Look-up table
Interconnection
Programmable Interconnection Points
Propagation delay
10
MEMORIES
The world of Memories
Static RAM memory (4T, 6T)
Decoder (low power)
Dynamic RAM memory
Embedded RAM
Sense ampli
ROM memory
EEPROM memory
FRAM memory
11
Analog Cells
5
20/12/03

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin