slyt340.pdf

Texas Instruments Incorporated

Power Management

Reducing radiated EMI in WLED drivers

By Jeff Falin

Senior Applications Engineer

Most mobile phones use white LEDs (WLEDs) as the

backlight for their displays. Li-Ion batteries with an output

range of 2.7 to 4.2 V are the most common power source

for mobile phones. Since several WLEDs in series, each

with forward voltages around 3.6 V, are typically used for

the backlight, the backlight driver must provide a voltage

higher than the Li-Ion range. Therefore, an inductive

boost converter is a common power-supply topology for

WLED drivers. Figure 1 shows a typical backlight-driver

solution that uses the TPS61161 to drive ten LEDs in series.

All inductive switching converters cause radiated electro-

magnetic interference (EMI) that is directly proportional

to output power. As the size of mobile phone displays

increases to accommodate more features, the backlight

driver’s increased output power results in more EMI.

Factors at each design step, from driver-IC selection to

board layout, impact the WLED driver’s EMI. Therefore,

minimizing the WLED backlight driver’s radiated EMI so

that it does not affect other systems is a major concern for

manufacturers of both the backlight driver IC and the

mobile phone.

Radiated EMI is caused by induced electric fields where

capacitors store their energy, and induced magnetic fields

where inductors store their energy. The electric-field

strength of a capacitor is directly proportional to its capac-

itance and the voltage across its terminals. The capacitance

is inversely proportional to the distance between the termi-

nals. Ideally, the IC and components are laid out on the

board to minimize the undesired (often called “parasitic”)

capacitance. Such capacitance can be created, for example,

by a large metal trace or plane on top of a ground trace or

plane. Likewise, an inductor’s magnetic-field strength is

directly proportional to its inductance value and the current

flowing through it. The inductance value is directly propor-

tional to the wire or trace length. The board ideally is laid

out to minimize parasitic inductance created by long wires,

loops, and traces; and shielded inductors are used on the

PCB itself. Moreover, the rate of change of the voltages

across and the currents through these parasitic compo-

nents directly impacts their field strengths. Key methods

of reducing EMI are to minimize the size of and interaction

between these parasitic components and to reduce their

voltages and current ramp rates.

The circuit designer and IC-layout engineer are respon-

sible for minimizing the parasitic inductances and capaci-

tances that occur at high frequencies (greater than

300 MHz) and/or for managing voltage and current ramp

ratesinsidetheIC.Otherwise,theICitselfwillgenerate

Figure 1. TPS61161 backlight driver

22 µH

3 to 18 V

1 µF

TPS61161

V IN

On/Off

Dimming

Control

CTRL

COMP

GND

Set



220 nF

L1: TDK VLCF5020T-220MR75-1

C1: Murata GRM188R61E105K

C2: Murata GRM21BR71H105K

D1: ONsemi MBR0540T1

20 mA

Analog Applications Journal

3Q 2009

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High-Performance Analog Products

Power Management

Texas Instruments Incorporated

EMI. Consider Figure 2, which shows the

drain voltage, V DS , of the TPS61161’s inter-

nalNMOSFET(i.e.,theswitchnode)as

the FET turns on. The blue trace is from a

test board with beta TPS61161 silicon that

has a commonly used high-speed gate drive.

The red trace shows the same node on the

same test board but with the final TPS61161

silicon that has TI’s dual-slope switching

technology. This technology controls the

switch node’s slope on the falling edge (i.e.,

dv/dt) in two steps. When the internal

power FET first turns on, there is a large

current spike. During the first step of a

dual-slope FET compared to a normal FET,

the dv/dt is slowed to reduce the amplitude

of the current spike and the EMI that

results primarily from parasitic inductance.

During the second step, the switch FET

returns to its normal, faster dv/dt to mini-

mize the switching losses that would other-

wise occur.

To measure the far-field EMI from a

battery-powered evaluation module

(TPS61161EVM-243), an IC with a tradi-

tional switch (shown in red in Figure 3) and

an IC with a dual-slope switch (shown in green) were used

in the same test environment. The black curve shows the

noise floor of the measurement, and the 850-MHz spike is

Figure 2. Switch node (V DS of NMOS FET) of TPS61161’s

WLED driver

First dv/dt

Second dv/dt

Dual-Slope Device

Performance

Beta Device

Performance

Time ( 2 ns/div )

from a spurious GSM signal. It is clear that the dual-slope

switching technology reduced the EMI in the 400-MHz

range by 10 dBµV/m.

Figure 3. TPS61161’s EMI measurements with traditional switch

and dual-slope switch

Spurious

GSM Signal

Traditional Switch

Dual-Slope Switch

Noise Floor

100

200

300

500 700 1000

Frequency (MHz)

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3Q 2009

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Power Management

Figure 4. Schematic of boost-converter-based WLED driver

Switch Node

C Par_D1

L Par1

L Par2

V IN

V OUT

Critical Loop

C OUT

C Par_Q1

Control

and

Gate Drive

C IN

Converter-IC GND

L Par4

At lower frequencies, the parasitic inductance and

capacitance of the PCB’s traces and planes are the primary

contributors to EMI. Figure 4 shows the schematic for a

boost-converter-based WLED driver. The loop created by

the parasitic capacitance of Q1 and D1 and the parasitic

inductance of the board traces conducts current when

switches D1 and Q1 turn on and off. When switch Q1 turns

off, inductor L1 is fully charged and ready to continue the

current flow. Since the only available element through

which current can continue to flow is D1, the inductor

voltage quickly switches from GND to V OUT , which causes

ringing due to the parasitics. The resonance point of the

parasitic inductance and capacitance can sometimes be

seen on the oscilloscope as ringing at the resonant fre-

quency. In addition to the parasitic capacitance of Q1 and

D1, ground planes and the traces over/under them also

contribute to parasitic capacitance. A commonly over-

looked type of parasitic capacitance is that formed by the

switch node—with its large dv/dt—and the ground plane

underneath. Figure 5 shows a poor PCB layout that uses

the TPS61161, where L1 is the inductor, D1 is the diode,

U1istheTPS61161controller,C1istheinputcapacitor,

and C3 and C4 are the output capacitors. The critical loop,

highlighted in blue, is long; and there is a large ground

plane underneath the large pad for L1 that serves as the

high-speed switch node (not shown).

Figure 5. Poor PCB layout with TPS61161

Switch

Node

Critical

Loop

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Figure 6. Improved PCB layout with TPS61161

Switch

Node

Critical

Loop

Figure 6 shows the TPS61161 evaluation module with

the same components as in Figure 5 but with a smaller

switch node, no ground plane underneath, and more com-

pact part placement to reduce the length of the critical

loop (shown in blue).

Figure 7 shows the near-field EMI measurements from

two battery-powered test boards, one with poor layout

and the other with improved layout. The tests were con-

ducted under identical conditions with the same inductor

and the TPS61161 (final silicon). Clearly, an improved

board layout that minimizes parasitic board capacitance

and inductance reduces EMI across multiple frequencies.

A switching converter’s EMI cannot be completely elimi-

nated. However, with careful IC and passive-component

selection as well as good board-layout techniques, EMI can

be reduced to acceptable levels.

Reference

For more information related to this article, you can down-

load an Acrobat ® Reader ® file at www-s.ti.com/sc/techlit/

litnumber and replace “ litnumber ” with the TI Lit. # for

the materials listed below.

Document Title

TI Lit. #

1. “White LED Driver With Digital and PWM

Brightness Control in 2mm × 2mm QFN

Package for up to 10 LEDs in Series,”

TPS61160/61 Data Sheet................... slvs791

Related Web sites

power.ti.com

www.ti.com/sc/device/TPS61161

Figure 7. TPS61161’s EMI measurements with poor and

improved layouts

23.5

Poor Layout

Improved Layout

21.5

19.5

17.5

15.5

13.5

11.5

9.5

0.1

100

1000

Frequency (MHz)

High-Performance Analog Products

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3Q 2009

Analog Applications Journal

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