20504di.pdf

design

ideas

Edited by Bill Travis

The best of

design ideas

Double DAC rate by using mixers as switches

Randall Carver, Analog Devices, Greensboro, NC

sample rate of a DAC by interleaving

two DACs into a single unit. Updat-

ing each DAC on an alternating basis and

switching to the appropriate output dou-

ble the effective throughput of the over-

all system. It is essential to overall per-

formance that you use a high-quality,

high-speed switch in the multiplexing of

the DACs’ outputs. The current-mode

DACs in this Design Idea allow for cur-

rent-steering implementation of the out-

put switch. Current steering uses two dif-

ferential-transistor pairs cross-coupled in

the form of a four-quadrant multiplier

( Figure 1 ). In this topology, the satura-

tion voltages of the transistors are mini-

mal, voltage swings are small, and switch-

ing speeds are high.

The 2.5-GHz AD8343 mixer contains

a complete four-quadrant-multiplier

structure that you can use as a high-

speed, current-mode switch. The bias

Double DAC rate by using mixers

as switches ...................................................... 69

DDS IC plus frequency-to-voltage converter

make low-cost DAC........................................ 70

Low-noise ac amplifier has digital control

of gain and bandwidth ................................ 72

1-kV power supply produces

a continuous arc ............................................ 76

OUTP

OUTN

SEL

Publish your Design Idea in EDN . See the

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INP

INN

circuitry internal to the AD8343 sets the

dc voltage at the emitters to approxi-

mately 1.2V, which in turn sets the com-

pliance voltage necessary at the DAC

You can use cross-coupled

differential transistor pairs as

current-mode switches.

Figure 2

DATA BUS A

D0-D9

IOUT

INP

INN

OUTP

IC 1

AD9731

10-BIT,

170M-SAMPLE/SEC

DAC

IC 5

AD8343

2.5-GHz MIXER

IC 3

90LV027A

LOP

CLK

OUTN

REF_IN

CA_OUT

CA_IN

REF_OUT

CL K

CLK

LON

RSET

1.96k

OUT

DATA BUS B

D0-D9

IOUT

INP

INN

OUTP

IC 2

AD9731

10-BIT,

170M-SAMPLE/SEC

DAC

IC 4

90LV027A

IC 6

AD8343

2.5-GHz MIXER

LOP

CLK

OUTN

REF_IN

CA_OUT

CA_IN

REF_OUT

C L K

CLK

LON

RSET

1.96k

“Ping-ponging” the outputs of two DACs effectively doubles the throughput rate.

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FEBRUARY 5, 2004 | EDN 69

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Y OU CAN EFFECTIVELY double the

Figure 1

design

ideas

outputs. With only a minimal drive sig-

nal at the base connections, the emitters

appear as a virtual ac ground. The re-

duced voltage swing at these nodes min-

imizes the effect of any parasitic capac-

itances. This Design Idea uses two

AD8343 mixers as high-speed switches

to multiplex the differential output cur-

rents derived from two AD9731 DACs

( Figure 2 ). On the output side of the

mixers, the termination resistors allow

for a dc path to the supply, provide for

the current-to-voltage conversion, and

. This configura-

tion allows the circuit to drive a re-

motely located, 100

, differential load

coaxial cables. The low-lev-

el clock signals at the LO inputs come

from high-speed LVDS buffers termi-

nated in resistances of 10

. The ap-

3.5-mA p-p drivers pro-

duce roughly 70-mV p-p drive at

the LO inputs. Figure 3 shows

that the circuit provides output rise and

fall times faster than 200 psec.

Figure 3

The circuit in Figure 2 produces outputs with

less-than-200-psec rise and fall times.

DDS IC plus frequency-to-voltage converter

make low-cost DAC

Noel McNamara, Analog Devices, Limerick, Ireland

P RECISION DACS are es-

V OUT

sential in many con-

sumer, industrial, and

military applications, but

high-resolution DACs can

be costly. Frequency-to-

voltage converters have

good nonlinearity specifi-

cations—typically, 0.002%

for the AD650—and are in-

herently monotonic. This

Design Idea shows how you

can use a frequency-to-

voltage converter and a

DDS (direct-digital-syn-

thesizer) chip for precise

digital-to-analog conver-

sion. The DDS chip gener-

ates a precision frequency

proportional to its digital

input. This frequency

serves as the input to a volt-

age-to-frequency converter,

thereby generating an 18-

bit analog voltage pro-

portional to the origi-

nal digital input. Figure 1

shows how the AD650 is

configured for frequency-to-voltage con-

version. With R 1

R 3

INPUT

OFFSET

TRIM

C INT

20k

AMP

R 1

250k

1 5 V

0.1

S 1

AD650

ANALOG

GROUND

V S

1 mA

15V

0.6V

V S

500

560 pF

0.1 F

f IN

OUT

500

FREQUENCY

ONE

SHOT

OUT

C OS

1N914

COMPARATOR

Figure 1

This circuit shows the AD650 in a frequency-to-voltage configuration.

R 3

20 k

and

Resolution of 18 bits requires a pro-

grammable clock source with a frequen-

cy resolution of 0.38 Hz (100 kHz/

262,144). The AD9833 low-power DDS

IC with on-chip 10-bit DAC is ideal for

this task, because setting the clock fre-

quency requires no external components.

The device contains a 28-bit accumula-

tor, which allows it to generate signals

with 0.1-Hz resolution when you operate

it with a 25-MHz master clock. Figure 2

shows a block diagram of the AD9833

DDS chip. Figure 3 shows the complete

system. The most significant bit of the

on-chip DAC switches to the V OUT pin of

the AD9833, thus generating the 0V-to-

620 pF, a full-scale input frequency

of 100 kHz produces a full-scale output

voltage of 10V. (See Analog Devices

(www.analog.com) application note AN-

279 for more details on using the AD650

as a frequency-to-voltage converter.)

70 EDN | FEBRUARY 5, 2004

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present a single-ended back-termina-

tion impedance of 50

via two 50

proximate

C OS

design

ideas

AG N D

DG N D

V D D

CAP/ 2 .5V

MCLK

ONBOARD

REFERENCE

REGULATOR

FULL-SCALE

CONTROL

AVDD/

DVDD

COMPARATOR

2.5V

MULTIPLEXER

FREQUENCY0 REGISTER

28-BIT PHASE

ACCUMULATOR

SIN

ROM

10-BIT

DAC

FREQUENCY1 REGISTER

MSB

MULTIPLEXER

PHASE0 REG

PHASE1 REG

V OUT

DIVIDE

BY 2

MULTIPLEXER

Figure 2

200

CONTROL REGISTER

MULTIPLEXER

SERIAL INTERFACE

AND CONTROL LOGIC

AD9833

FSYNC SCLK SDATA

This DDS chip generates signals with 0.1-Hz resolution from a 25-MHz clock.

V DD square wave that serves as the clock

input to the AD650 voltage-to-frequen-

cy converter. Writing to frequency-con-

trol registers via a simple three-wire in-

terface sets the clock frequency,

thus programming the voltage out-

put.

FSYNC

SCLK

SDATA

MCLK

V OUT f IN

AD650

VOLTAGE-

TO-FREQUENCY

CONVERTER

V OUT =0 TO 10V,

18-BIT RESOLUTION

MICROCONTROLLER

AD9833

DDS

Figure 3

This DAC system delivers 0 to 10V output with 18-bit resolution.

Low-noise ac amplifier has

digital control of gain and bandwidth

Philip Karantzalis, Linear Technology, Milpitas, CA

gain amplifier serves at the input to

increase the SNR. The input signal

level determines the input-stage gain;

low-level signals require the highest gain.

It is also standard practice in low-noise

analog-signal processing to

make the circuit’s bandwidth

as narrow as possible to pass only the

useful input-signal spectrum. The opti-

mum combination of an amplifier’s gain

and bandwidth is the goal of a low-noise

design. In a data-acquisition system, dig-

ital control of gain and bandwidth pro-

vides dynamic adjustment to variations

in input-signal level and spectrum. Fig-

ure 1 shows a simplified circuit for an ac

R 2

C 2

V I N

C 1

R 1

V O UT

Figure 1

GAIN-

CONTROL PGA

(GAIN A)

BANDWIDTH-

CONTROL PGA

(GAIN B)

GAIN=–1

NOTES:

V OUT =(GAIN A)V IN .

2 R 1 C 1

BANDWIDTH

R 2 C 2

(GAIN B)

This ac-amplifier configuration offers both gain and bandwidth control.

72 EDN | FEBRUARY 5, 2004

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I N LOW-NOISE ANALOG circuits, a high-

design

ideas

C 1

R 1 R 2

15.8k 15.8k

V OUT

Figure 2

0.1

C 2

R 4

IC 1

IC 2

IC 3

15.8k

LTC6910-1

LT1884

LTC6910-1

V IN

R 3

0.1

15.8k

GAIN

CONTROL

BANDWIDTH

CONTROL

V OUT

V IN

GN2 GN1 GN0

BANDWIDTH

1 TO 10 Hz

BW2 BW1 BW0

V OUT

V IN

BANDWIDTH

1 TO 20 Hz

BANDWIDTH

1 TO 50 Hz

V OUT

V IN

BANDWIDTH

1 TO 100 Hz

V OUT

V IN

BANDWIDTH

1 TO 200 Hz

V OUT

V IN

1 TO 500 Hz

BANDWIDTH 1Hz TO 1 kHz

V OUT

V IN

V OUT

100

V IN

This detailed implementation of the circuit in Figure 1 operates with dual power supplies.

amplifier with control of

both gain and bandwidth.

The amplifier’s input is a

PGA (programmable-gain

amplifier) providing gain

control (Gain A). Following

the input PGA is a first-or-

der highpass filter formed

with capacitor C 1 and input

resistor R 1 of an integrator

circuit. Inside the integra-

tor’s feedback path, the gain

of a second PGA (Gain B)

multiplies the integrator’s

to provide high SNR. For ex-

ample, the SNR is 76 dB for

a 10-mV peak-to-peak signal

with a gain of 100 and 100-

Hz bandwidth or 64 dB for

a 100-mV peak-to-peak sig-

nal with a gain of 10 and 1-

kHz bandwidth. With an

LT1884 dual op amp (gain-

bandwidth product of 1

MHz), the circuit’s upper

frequency response can in-

crease to 10 kHz by reducing

the value of C 2 . (The lower

BW2 BW1 BW0

GAIN

(dB)

BW2 BW1 BW0

0 0 1

BW2 BW1 BW0

1 0 0

3-dB frequency, thus pro-

viding bandwidth control.

Figure 2 shows a com-

plete circuit implementa-

tion using two LTC6910-1

digitally controlled PGAs

and an LT1884 dual

op amp. The input

LTC6910-1, IC 1 ,provides

digital gain control from 1 to 100 using

a 3-bit digital input to select gains of 1,

2, 5, 10, 20, 50, and 100. The circuit’s low-

3-dB frequency increases

by reducing the value of C 1 .)

The circuit in Figure 2 oper-

ates with

5.5V dual power

supplies. You can convert it

to a single-supply 2.7 to 10V

circuit by grounding Pin 4 of

IC 1 ,IC 2 , and IC 3 ; connecting

a 1-

100

10k

100k

FREQUENCY (Hz)

Figure 3

The frequency response of Figure 2’s circuit shows unity gain

and three digital bandwidth-control inputs.

F capacitor from Pin 2

of IC 1 to ground; and connecting Pin 2

of IC 1 to pins 3 and 5 of IC 2 and Pin 2 of

IC 3 . Figure 3 shows the frequency re-

sponse of the circuit in Figure 2 with

unity gain and three digital bandwidth-

control inputs.

The integrator’s digital gain control be-

comes digital bandwidth control, which

provides an upper

3-dB frequency

control of 10 Hz to 1 kHz. The circuit’s

low-noise LT1 884 op amp and LTC6910-

1 (9 nV/

3-dB frequency is fixed and set to 1

Hz. A second LTC6910-1, IC 3 , is inside

an LT1884-based (IC 2 ) integrator loop.

Hz for each device) combine

74 EDN | FEBRUARY 5, 2004

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BANDWIDTH

design

ideas

1-kV power supply produces a continuous arc

Robert Sheehan, Linear Technology, Milpitas, CA

ing power supply that can produce

a sustained arc can be challenging.

This compact and efficient design deliv-

ers 1 kV at 20W and can withstand a con-

tinuous arcing, or short-circuit, condi-

tion ( Figure 1 ). It uses standard, com-

mercially available components. R 1 sets

the LTC1871 switching-regulator con-

troller for a nominal operating frequen-

cy of 120 kHz. The circuit operates as a

discontinuous flyback structure, produc-

ing 333V across C 1 . The diode/capacitor

charge-pump multiplier triples this volt-

age to create 1000V at the output. Figure

2 shows the switching waveforms. When

the primary switch, Q 1 , is on, the output

rectifiers are reverse-biased, and energy is

stored in the transformer, T 1 . When Q 1

turns off, energy transfers to the second-

ary winding, and C 2 and C 3 pump up the

output voltage through the rectifiers. The

primary voltage goes high and is clamped

through the transformer

and rectifier, D 1 , by the

voltage across C 1 .The

transformer is well-cou-

pled, so the leakage in-

ductance creates little

voltage spike. A small RC

snubber across the pri-

mary winding damps the

ringing and reduces EMI

(electromagnetic inter-

ference).

For current-limit pro-

tection, the circuit

in Figure 1 contains

two active circuits and

one passive element. The

voltage across the cur-

rent-sense resistor, R 2 ,

limits peak primary cur-

rent to 7.5A. Q 2 provides secondary-side

current limit. Notice the bump on the

leading edge of the current ramp of Trace

Figure 2

These are the switching waveforms for the circuit

in Figure 1. Channel 1is the primary-switch volt-

age at T 1 , Pin 12; Channel 2 is the primary-switch current into Q 1

drain (10A/division); Channel 3 is the secondary-switch voltage

at T 1 , Pin 2 (200V/division); Channel 4 is the voltage across R 3 .

(Secondary-switch current=2V/1.5 =1.33A/division.)

2 in Figure 2 . This bump coincides with

the positive excursion of the voltage

across R 3 in Trace 4, which is the refresh

WARNING: LETHAL VOLTAGE POTENTIALS!

Figure 1

C 2

C 3

0.022

R 4

100

500V

V IN

9 TO 18V DC

D 1

D 2

D 3

D 4

D 5

1 kV O UT

T 1

1/4W

4.99M

10 F

25V

10 F

25V

10 F

25V

220 pF

200V

0.022 F

500V

0.022 F

500V

68.1k

4.99M

C 1

0.022 F

500V

0.01 F

1500V

0.01 F

1500V

100

RUN

SENSE

I TH

IC 1

LTC1871

V IN

Q 1

Si7456DP

INTV CC

1 nF

FREQ

GATE

33k

R 1

220k

Q 2

VN2222

12.4k

MODE

GND

12.4k

6.8 nF

R 2

0.02

4.7 F

R 3

1.5

NOTES: D 1 , D 2 , D 3 , D 4 , D 5 : MURS160.

T 1 : COPPER VP5-0155.

This circuit delivers 1 kV from a low-voltage input and can produce continuous arcing.

76 EDN | FEBRUARY 5, 2004

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