51304di.pdf

design

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Edited by Bill Travis

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Circuit forms simple, low-cost, 1-kV driver

Tai-Shan Liao and Prasit Champa, National Science Council, Hsinchu, Taiwan

ly received much attention, because

they play an important role in driv-

ing piezoelectric and electro-optical

components, for example. Figure 1 shows

a simple, low-cost, 1-kV driver. The cir-

cuit uses offline, current-mode-control

techniques and a flyback switching-pow-

er-supply design. IC 1 , a UC3844, is the

major control component, using a

switching frequency of 100 kHz. The IC

provides frequency modulation to reduce

the switching frequency under light- and

no-load conditions. The feedback volt-

age, which you derive from the output of

the error amplifier, serves as the indica-

tor for load conditions. Once the feed-

back voltage becomes lower than the

green-mode threshold voltage, the

switching frequency starts to decrease.

All the power losses are in direct pro-

portion to switching frequency. These

losses include the switching losses of the

transistor, core losses in the transformer

and inductors, and the power loss of the

snubber. The frequency modulation in

the PWM-controller IC reduces the pow-

er consumption in the supply under

Circuit forms simple, low-cost,

1-kV driver ........................................................ 87

Make a printer-port EEPROM

programmer and dongle ............................ 88

Circuit controls ratiometric or simul-

taneous power-up of multiple rails............ 90

Scheme provides automatic

power-off for batteries .................................. 92

Publish your Design Idea in EDN . See the

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EI-25-2E6

CORE

1000V

450V

470k

T 1

TURNS

T 2

105

TURNS

110V AC

+ 220

0.1 F

100k

47 F

450V

470k

30k

400V

D 1

BR 1

FR137

450V

470k

FR137

T 3

105

TURNS

47 F

450V

470k

T 5

FIVE

TURNS

22 F

25V

0.1

T 4

SIX

TURNS

0.1

25V

130k

Q 1

IRF840

10O pF

IC 1

UC3844

FR137

V RE F

30O pF

33k

PC817

200

VR 1

500k

15k

R 5

6.8 nF

10k

Figure 1

0.1 F

2.2 nF

A PWM-controller IC

forms the heart of a

low-cost, regulated,

1-kV-dc supply.

IC 2

TL431

VR 2

10k

www.edn.com

MAY 13, 2004 | EDN 87

H IGH-VOLTAGE DRIVERS have recent-

design

ideas

light- and no-load conditions. But the

frequency modulation has no effect on

the PWM operation under normal- and

high-load conditions.

Pin 2 (the feedback pin) of the UC3844

sums the current-sense signal, the output-

voltage feedback signal, and any added

slope compensation. The feedback-con-

trol circuit uses a TL431 adjustable shunt

regulator to detect the output signal. A

PC817 passes the signal to the feedback

pin of the UC3844. The TL431 acts as an

open-loop error amplifier with a 2.5V

temperature-compensated reference.

When the output voltage is lower than the

desired level, the feedback to the UC3844

automatically compensates the pulse-

width modulation of the output trigger-

ing signal. Ceramic bypass capacitors (0.1

prevent core saturation, the gap is ap-

proximately 1 mm. The primary winding

has 70 turns of 28-gauge wire. Both the

secondary windings have 105 turns of 34-

gauge wire. The primary and secondary

auxiliary windings have five and six turns,

respectively, of 34-gauge wire. The dc out-

put voltage of the circuit in Figure 1 is 1

kV (fixed). You can adjust the output volt-

age in a 50V range by adjusting VR 1 . Both

load and line regulation are less than 1%,

and power efficiency is 80% at full load.

Make a printer-port EEPROM programmer and dongle

GY Xu, XuMicro, Houston, TX

er port for serial-EEPROM pro-

gramming. You can use a de-

vice-programmer circuit used to

program the MicroWire serial EE-

PROM 93CXX ( Figure 1 ). The cir-

cuit is so simple that any further

simplification seems impossible.

This programmer circuit contains

no microcontroller, as most device

programmers do. It needs neither a

separate power supply, or “wall-

wart,” nor a cable. When in use, it di-

rectly plugs into the PC’s printer

port. However, you still can use a ca-

ble if convenient—for PC printer

ports behind the PC, for example.

The circuit also requires neither a

resistor nor a decoupling capacitor.

These advantages come from the

PC’s printer-port resources and

the architectural simplicity of the

MicroWire serial EEPROM. The

printer port comprises the 8-bit

data, status, and control registers. Each

classic IBM PC, the data port serves sole-

ly for output, but the control port can

serve as either input or output. The eight-

pin, tiny, serial EEPROM consumes less

than 1-mA current in the active state, and

the printer port’s data pin can supply a

few milliamps, so this design uses D7 (Pin

9) as a power-supply pin. No decoupling

capacitor is necessary in practice.

The MicroWire chip uses the CS (chip-

select), SK (clock-signal), DI (data-input),

and DO (data-output) pins to control its

Once you settle on the hardware

design, the main task is to write

software. This task is not difficult.

For many embedded-system-soft-

ware engineers, it’s routine and in-

teresting. A freeware executable

program, Pseep2.exe, is available

for this purpose. A sample demo

program, secret.bin, allows you to

practice the programming. You can

download the software from the

Web version of this Design Idea at

www.edn.com. It handles only one

MicroWire device—the popular

93C46’s read/write operation as an

example. Another important fea-

ture of this circuit is that, once you

program the 93CXX device, the

system becomes a primitive don-

gle. You can then use it as a hard-

ware-protection device for your

valuable software. Only you know

whatever was programmed in the

device.

When the protected software runs, it

first checks whether the device is present

at the printer port and whether the code

matches what you programmed. If a

match doesn’t exist, the software refuses

to continue and exits. The dongle is

primitive, but it does illustrate the basic

principle of dongle-protection technolo-

gy. You can build the circuit using wire-

wrapping or point-to-point soldering

techniques on a solderless breadboard, in

which case you’ll need a cable, or with

your own pc board. It’s a one-evening

project.

V CC

9 D7

93CXX

ORG

GND

DB-25M

CONNECTOR

This printer-port serial EEPROM program-

mer can also act as a dongle once you program the device.

read/write operations. This design uses the

chip-select signal from the reverse level of

the control bit C3 (Pin 17). It also ties to-

gether pins DI and DO and connects them

to the Control bit C0 (Pin 1), which can

serve as input or output, thereby saving

one pin. These selections caused no prob-

lems in practice. Because control Pin 1’s

logic is the reverse of the logic level on bit

C0, the software must take care of the in-

version. The MicroWire interface nor-

mally requires a pullup resistor on the DO

pin, but such a resistor is already inside the

PC, so it’s unnecessary.

88 EDN | MAY 13, 2004

www.edn.com

F) from V CC and V REF to ground provide

low-impedance paths for high-frequen-

cy transients. This design uses a Tomita

(www.tomita-electric.com) EI25-2E6

core set to fabricate the transformer. To

Y OU CAN EASILY USE a PC’s print-

Figure 1

design

ideas

Circuit controls ratiometric or simultaneous

power-up of multiple rails

Dirk Gehrke, Texas Instruments, Freising, Germany

M ANY APPLICATIONS use FPGAs,

IC 2 controllers share a soft-start capaci-

tor, C 14 . This example uses two buck con-

verters with integrated synchronous-

rectification FETs. From a 5V

input-voltage rail, IC 1 generates the 3.3V

I/O voltage. Buck converter IC 2 gener-

ates the 1.5V output voltage.

The soft-start pin, available on both

controller ICs, serves two purposes. You

can use it to enable the controller cir-

cuitry if required—an implementation

you could realize by tying an open-col-

lector or open-drain gate to the SS Pin.

If the transistor or FET is active, it

ties the SS Pin to ground potential,

forcing both controllers to stay off. Once

you release the SS Pin, both ICs start to

charge C 14 with their internal 5-

ASICs, or DSP chips, which usual-

ly require multiple voltage rails,

typically two: the core voltage and the I/O

voltage. The core voltage is usually lower

than the I/O voltage. Guidelines for de-

termining how to power up two or more

voltage rails depend on the part and the

manufacturer you use. The first imple-

mentation in Figure 1 shows how to re-

alize ratiometric sequencing, which

means that both power-supply output

rails simultaneously start and simultane-

ously reach their final regulated output

voltage. This implementation uses resis-

tor R 15 connected to ground; the path and

components in red are deleted. You can

achieve the ratiometric function by stack-

ing together multiple converters that

share one soft-start capacitor. This con-

nection ensures that both controllers

ramp up their output voltage at the same

time during power-up. Both the IC 1 and

0.2 mSEC

0.50V

0.2 mSEC

0.50V

0.2 mSEC

1 10 mV 50

2 50 mV DC

3 50 mV DC

4 0.1V DC

10 MSAMPLES/SEC

2 DC 2.00V

□

STOPPED

Figure 2

This graphic shows measurement results for

the ratiometric implementation.

A cur-

A current flows

into C 14 . Once C 14 reaches the threshold

voltage of 1.2V, both controllers start to

operate. You can easily calculate the de-

lay versus the capacitor’s value: Delay

A). As the output ac-

tivates, a brief ramp-up at the internal

soft-start ramp may occur before the ex-

ternal soft-start rate takes control. The

output then rises at a rate proportional

C 14 (1.2V/10

V IN 5V

L 1

I/O 3.3V, 3A

V IN

R 1

76.8k

C 1

470

C 2

10 F

C 6

47 nF

C 7

C 8

R T

C 12

1.8 nF

R 7

105

C 5

100 nF

BOOT

TPS54310

IC 1

V BIAS

C 13

56 p F

R 8

27.4k

V SENSE

SYNC

R 2

3.83k

C 10

6.8 nF

R 9

D 1

COMP

R 3

40.2k

R 15

10.22k

GND

R 6

13.7k

C 9

470 pF

R 5

330k

Q 1

C 11

L 2

CORE 1.5V, 6A

V IN

R 4

330k

C 19

47 nF

C 20

47 F

C 21

47 F

PGOOD

BOOT

C 18

5.6 nF

R 13

33.2

TPS54610

IC 2

Figure 1

V BIAS

SYNC

V SENSE

R 14

10k

R 10

71.5k

This circuit provides

ratiometric (delete red

path and components) or

simultaneous power-up

sequencing.

C 17

18 nF

C 15

100 nF

R 11

COMP

GND

R 12

14.7k

C 14

39 nF

C 16

1.5 nF

90 EDN | MAY 13, 2004

www.edn.com

rent sources. In total, 10-

time

design

ideas

to the soft-start capacitor. You can pro-

gram the soft-start time via C 14 . The next

equation represents the soft-start time

calculation. The actual soft-start time is

likely to be less than the calculated ap-

proximation because of the brief ramp-

up at the internal rate. Soft-start

time

C 14 (0.7V/10

A). If you set IC 1 for

start at the same time with the same

ramp, reaching their final value at the

same time. Once both rails reach 1.5V,

you must increase IC 1 ’s output voltage to

3.3V, its final value. To make that increase

happen, Q 1 places R 6 in parallel with R 3 .

You can calculate the value of R 6 using the

next three equations. The given parame-

ters are: V OUTCORE

parator output pin. This action forces the

pin to rise immediately to the output-

voltage level because of resistor R 4 ’s

pullup action. A lowpass filter consisting

of R 5 and C 11 forms a delay circuit, driv-

ing MOSFET transistor Q 1 ’s gate. This

delay circuitry determines when Q 1 be-

comes active. Q 1 has a threshold voltage,

V GSTH , of 1.6V. Once the gate voltage

reaches or exceeds the threshold voltage,

V GSTH ,Q 1 starts to conduct, putting R 6 in

parallel with R 3 . Because of the resistor-

ratio change, IC 1 ’s output voltage ramps

up to its final I/O-voltage value of 3.3V.

The MOSFET this design uses has an on-

resistance of roughly 10

1.5V; R 8

27.4 k

;

0.891V, the internal bandgap-ref-

erence voltage of IC 1 ; and R 3

5 mSEC

0.50V

You can program V OUTI/O via R 8 and R X .

R X represents the value of R 3 and R 6 in a

parallel connection.

40.2 k

5 mSEC

0.50V

. This figure

might sound high, but, because of the

high-ohmic-resistive divider, this value

does not affect performance. Figure 3

shows the results of the described imple-

mentation during power-up.

Significantly, in this implementation

both converters run at the same switch-

ing frequency. IC 2 is the master con-

troller, programmed to a 700-kHz

switching frequency. IC 1 starts at a lower

initial switching frequency of roughly

630 kHz, 10% below the switching fre-

quency of IC 2 . Once IC 2 begins to oper-

ate, it synchronizes IC 1 via the Sync Pin.

Diode D 1 limits negative voltage spikes at

the Sync input. Placing a well-chosen

Schottky diode between both output

voltage rails can ensure that, even during

power-down, both rails have a voltage

difference of 400 to 600 mV for safety

reasons. The cathode connects to the I/O-

voltage rail, and the anode connects to

the core rail.

5ms

1 10 mV 50

2 50 mV DC

3 50 mV DC

4 0.1V DC

500 kSAMPLES/SEC

2 DC 1.02V

□

STOPPED

Figure 3

These curves, distinctly different from those in

Figure 2, show simultaneous-sequencing

results.

R X must have a value of 10.22 k

to pro-

duce V OUTI/O

3.3V.

3.3V and IC 2 for 1.5V, they both reach

their final voltage level at the same time.

Figure 2 shows measured results of the ra-

tiometric sequencing.

In the simultaneous-sequencing sce-

nario, IC 2 acts as the master controller.

You program its output voltage via R 14

and R 12 to a value of 1.5V. R 8 and R 3 pro-

gram the slave controller IC 1 ’s output

voltage to a value of 1.5V. As the ratio-

metric scenario describes, both voltages

In this example, R 6

needs a value of

. Applying 5V to the input-volt-

age rail activates both controllers at once,

allowing them to start at the same time.

Once the master controller, IC 2 , reaches

an output voltage level equal to or greater

than 90% of the initial value, the IC re-

leases the power-good open-drain-com-

Scheme provides automatic power-off for batteries

Miguel Gimenez, Altair-Equipos Europeos Electronicos, Madrid, Spain

T HE CIRCUIT IN Figure 1 provides a

simple and inexpensive way to pro-

tect one of the most valuable com-

ponents in portable applications: the bat-

tery. Applications include all portable

equipment that requires a limited time of

operation, such as test instruments, gui-

tar tuners, and electronic toys. Pressing

the on/off momentary switch starts the

cycle, and the circuit provides power to

the application circuit. If you again press

the switch at any instant, the circuit

switches off and “sleeps” until the next

cycle. In case you forget to switch off the

circuit, the circuit incorporates an auto-

power-off function with a time period

that is a function of preprogrammed

time constants.

IC 1 and related parts provide a bistable

toggle function and also ensure protection

against switch-contact bounce. IC 1C

buffers the toggled signal and isolates the

R 1 -C 1 charging current. This signal feeds

the IC 2 timer, configured as a monostable

multivibrator that remains activated un-

til it times out, according to the expression

is approximately six minutes. The timer’s

output feeds the Q 1 inverter that activates

medium-power, pass-through Q 2 transis-

tor. This circuit is configured as a pnp

block to ensure low losses to the load. The

loss comes only from V CE(SAT) —approxi-

mately 0.2V at 100 mA, or 20 mW. For ap-

plications demanding more current, you

can choose a more suitable transistor. A

MOSFET can be an efficient approach

when you need either lower standby loss-

es or a lower voltage drop between the bat-

tery and the application circuit.

Standby losses in the switched-off state

R T C T . This figure is the auto-pow-

er-off time. In the example, this interval

92 EDN | MAY 13, 2004

www.edn.com

V REF

13.7 k

1.1

design

ideas

V IN

9V DC

BATTERY

Q 2

BD140

V OUT

–

C 6

1 F

R 9

100k

APPLICATION

R 3

22k

IC 1A

CD4023A

R 2

2.2k

IC 1B

CD4023A

IC 1C

CD4023A

R 7

2.2k

D 1

LED

R T

R 4

100k

R 5

100k

R 6

10k

R 1

390k

VCC

Q 1

BC337

S 1

TRIGGER

RESET

CONTROL

THRESHOLD

DISCHARGE

OUTPUT

IC 2

C 1

100 nF

ON/OFF

MOMENTARY

C T

330

C 2

1 nF

C 3

10 nF

C 4

10 nF

GND

Figure 1

C 5

10 nF

555

This battery-saving circuit is handy for applications requiring a limited operating time.

OFF

are negligible, because the circuit draws

power only from the CMOS gate in the

inactive off-state. LED D 1 indicates the

on-off status of the circuit. No extra pow-

er comes from the battery to drive this

LED, because it is connected in the cur-

rent-source leg of the driver transistor.

The output transition to 0V during time-

out ensures the timed power-off by

means of the C 5 feedback loop that tog-

gles the bistable circuit to the off state,

performing the same role you might have

forgotten with the on/off switch. This

simple circuit is useful when the applica-

tion doesn’t require a microcontroller.

94 EDN | MAY 13, 2004

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