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Circuit produces variable numbers of burst pulses

Michael Kornacker, Northrop Grumman Corp, Rolling Meadows, IL

produce one to 15 burst pulses with

the same number of spaces between

the bursts at a pulse width (frequency)

that an external square-wave generator

at the input sets. The add-on circuit

produces a variable number of bursts

and a variable number of spaces be-

tween the bursts by using an external

square-wave generator as a source. The

project in this design required a TTL

burst signal, but resources did not allow

for the expense of a burst generator. The

circuit basically comprises two hexa-

decimal, divide-by-16 counters set up

so that the counter on the left produces

a user-selectable zero to 15 pulses and

the counter on the right produces a

user-selectable zero to 15 spaces. The

two hexadecimal thumbwheel switches

select the number of pulses and spaces.

Counter IC 1 controls the number of

bursts, and counter IC 2 controls the num-

ber of spaces. The two hexadecimal

thumbwheel switches, S 1 and S 2 , select the

count value. Each switch position is num-

bered zero to 15. S 1 controls the number

of burst pulses, zero to 15, and S 2 controls

the number of spaces, zero to 15. For ei-

ther the IC 1 or the IC 2 counter to count,

Pin 7 must be high. If Pin 7 is low, then the

counter remains disabled. For a counter to

be loaded with a desired count, Pin 9 must

be low and then high. The carry output at

Pin 15 is normally low until the counter

reaches a count of 15, and then it goes

high. When the circuit is powered on, re-

sistor R 1 and capacitor C 1 form an RC-

time-constant power-on-reset circuit at

Pin 1. This feature initializes the counters

Circuit produces variable numbers

of burst pulses ................................................ 79

Method provides fast, glitch-free isolation

of I 2 C and SMBus signals ............................ 80

Simulate input-offset current

for current mirrors.......................................... 84

Designing high current chokes

is easy .............................................................. 84

Publish your Design Idea in EDN . See the

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to the zero state upon power-up. After

that, the thumbwheel switches set the

count value.

When a clock signal arrives at the

counters’ Pin 2 with the desired fre-

quency, counter IC 1 starts counting up,

and counter IC 2 re-

mains in the off-state

because the low signal

at IC 1 ’s Pin 15 carry

output applied to IC 2 ’s

Pin 7 disables counter

IC 2 . When IC 1 ’s count

reaches the end (15), it

goes high and enables

IC 2 to count. IC 1 ’s car-

ry output also goes

through inverter gate

IC 3A and then to the

OR gate IC 4 ’s Pin 1.

The low signal on one

input of IC 4 —and the

fact that, because IC 2 is

now counting, its car-

ry output at Pin 15 is

also low at IC 4 ’s Pin

2—means that a low

signal appears at IC 1 ’s

Pin 7, and thus IC 1

now becomes dis-

abled. Both IC 1 and

IC 2 counters’ Enable

pins are cross-con-

S 1

S 2

0-F H PULSES

0-F H SPACES

R 2

4.7k

R 6

R 7

R 8

R 9

4.7k

R 3

R 4

R 5

4.7k

R 2

4.7k

16 10

V CC T

5 4 3

16 10

543

C 1

D2 D1

CLR

V CC T

D2 D1

CLR

FREQUENCY

INPUT

IC 3A

7404

IC 1

74161

CLK

IC 2

74161

CLK

CAR

GND

IC 3B

7404

Figure 1

7432

IC 4

GATE

3 BURST OUTPUT

7400

IC 5

This circuit produces a variable number of burst pulses and spaces.

www.edn.com

JUNE 24, 2004 | EDN 79

T HE ADD-ON CIRCUIT in Figure 1 can

design

ideas

nected, so that when one counter is

counting, the other counter becomes dis-

abled. The two counters work in this

way, back and forth, counting up to 15

and enabling and disabling each other.

And finally for the two counters, when

the carry output on IC 2 goes high, the

circuit then, after it reaches a count of 15

through the inverter IC 3B , loads a new

count or reloads the old count into the

counters as set by the thumbwheel

switches for the next count.

When IC 1 is counting, the output of

IC 3A (the gate signal), assumes a high

level at AND gate IC 5 ’s Pin 2. This state

allows the clock signal to pass through

IC 5 unimpeded to the output. The out-

put of IC 5 is the burst output. When IC 1

is disabled and IC 2 is counting, the gate

signal from IC 3A asserts a low signal at

IC 5 ’s Pin 2. The output is also low and

produces no bursts. You can configure

this circuit to produce even more puls-

es or spaces by simply cascading more

counter chips where needed. Also, you

can replace switches S 1 and S 2 by an 8-

bit write-output register, making the

pulse and space counts software-con-

trolled, or you could apply the gate sig-

nal to the control input of a CMOS

switch to burst analog signals, such as

sine waves at its input.

Method provides fast, glitch-free

isolation of I 2 C and SMBus signals

Mark Thoren, Linear Technology Corp, Milpitas, CA

I 2 C IS A POPULAR SERIAL protocol for

power controllers, ADCs and DACs,

EEPROMs, and other devices. In cer-

tain data-acquisition and power-control

situations, you must isolate the I 2 C

master from one or more slave de-

vices for noise, grounding, or safety is-

sues. Also, although 128 peripherals may

connect to the bus, at some point, differ-

ences in ground potential and excessive

bus capacitance begin to erode noise and

timing margins. This Design Idea shows

how to provide fast, glitch-free optical

isolation of I 2 C or SMBus signals by us-

ing a method that meets the require-

ments for the 400-kHz enhanced-I 2 C-

bus specification. The I 2 C bus consists of

bidirectional clock and data lines (SCL

and SDA) that are pulled up with resis-

tors or current sources. Devices connect

to the bus with open-collector I/O pins.

One way to isolate I 2 C signals is with a

variation of the circuit shown in Figure

1 , which shows only SDA; SCL operation

is identical.

The circuit in Figure 1 works on the

principle that a device pulling the non-

isolated SDA line low turns on an opto-

coupler LED, pulling the isolated SDA

line low and disabling the isolated side’s

optocoupler LED and vice versa. Howev-

er, if devices on both sides of the isolation

barrier are pulling their respective SDA

lines low, the optocouplers are in an in-

determinate state, with both LEDs par-

tially on. When the nonisolated device re-

Figure 1

BAT85

ISOLATED SDA

HCPL2300#300

74HC125

BAT85

ISOLATED

GROUND

SDA

HCPL2300#300

74HC125

ISOLATED

GROUND

This circuit represents a simple I 2 C isolator.

leases its SDA line, the voltage on the line

rises until the isolated side’s LED can turn

fully on. Only then will the nonisolated

SDA line go low again. This situation oc-

curs at various times during I 2 C com-

munications, including clock synchro-

nization (on the SCL line), multimaster

arbitration, and SMBus interrupt arbi-

tration (on the SDA line). Figure 2 shows

details of the operation of the circuit in

Figure 1 . The 74HC125 tristate nonin-

verting buffers simulate the open-drain

out puts of two I 2 C devices. A logic low on

the EN line forces the output low, and a

logic high puts the output in a high-im-

pedance state. Traces 1 and 2 show the

inputs to the enable lines of the SDA and

isolated-SDA buffers. Traces 3 and 4 show

the outputs, respectively.

This type of circuit has been pub-

lished in a number of forms, often with

slow optocouplers that require 5 to 10

mA of LED drive. These circuits may

work in a limited set of applications, but

they are slow and still produce glitches,

and trying to overcome speed and drive

issues with high-speed components

makes the circuits almost unusable. The

80 EDN | JUNE 24, 2004

www.edn.com

design

ideas

of LED drive. If both SDA lines are held

low and then released at the same time,

the optocouplers fight each other and

form an oscillator ( Figure 3 ). The char-

acteristics of this oscillation depend on

When both sides are idling high, both

optocouplers are off. When one side

pulls its line below 0.4V (a safe assump-

tion for both open-collector and open-

drain outputs), the comparator turns on

its LED. The other side’s line pulls down

to approximately 0.6V, which is still in-

terpreted as a logic low but does not re-

sult in that side’s LED turning on. When

both sides are pulling their lines low,

both LEDs are on. In this state, if one side

releases its line, it rises cleanly from the

low level of the I 2 C device’s output to ap-

proximately 0.6V.

Figure 5 shows details of the op-

eration of the circuit in Figure 4 .The

combination of the LT1719 compara-

Figure 5

This scope photo shows the

operation of the improved

I 2 C isolator.

tor and Agilent (www.agilent.com)

HCPL2300 optoisolator meets the tim-

ing requirements of the 400-kHz en-

hanced I 2 C-bus specification. Total

propagation delay is approximately 100

nsec, and you can adjust the logic

thresholds to suit other requirements.

Although you can use this circuit for

both SDA and SCL lines to support full

clock synchronization, the extra cir-

cuitry is unnecessary as long as the

master never tries to communicate

faster than the slowest slave device. If

you don’t need clock synchronization,

you can use a single optocoupler for

SCL.

The simple I 2 C isolator pro-

duces large glitches under

some circumstances.

pullup resistance, supply voltage, and

capacitance on the data lines. (Remov-

ing one of the 9-pF scope probes stops

the oscillation, and replacing it with a

10-pF capacitor starts it up again.)

The circuit shown in Figure 4 solves

these problems by setting up three

logic levels: “high” (pulled up to 5V),

“pulling low,” and “being pulled low.”

Figure 3

Using high-speed components

in Figure 1’s circuit causes

unpredictable behavior.

ISOLATED 5V

SDA

LT1719

74HC125

169

V+

7.5k

11.5k

(0.4V)

HCPL2300

SHDN

ISOLATED 5V

ISOLATED

GROUND

ISOLATED

GROUND

LT1719

ISOLATED SDA

V+

Figure 4

11.5k

7.5k

169

74HC125

(0.4V)

The improved I 2 C

isolator is fast

and produces no

glitches.

SHDN

HCPL2300

ISOLATED

GROUND

82 EDN | JUNE 24, 2004

www.edn.com

circuit in Figure 1 uses fast HCPL2300

optocouplers that require only 500

Figure 2

design

ideas

Simulate input-offset current for current mirrors

Johan Bauwelinck, Gent University, Gent, Belgium

S IMULATING THE OUTPUT-offset cur-

matches, and so on, the in-

put offset current is not

equal to zero. The design in

Figure 1 provides high ac-

curacy and a low simulation

time.

You use feedback to force

the current of a CCCS (cur-

rent-controlled current

source) to equal the input-

offset current. The current

that flows into voltage

source V OUT is the difference

between the output current

of the mirror and the

ideal output current.

This current is the “error

current” (I ERROR ). When the

CCCS equals the input-

offset current, then the

error current is zero. The

high-gain CCCS ampli-

fies the error current, and

the CCCS adds to the in-

put current. In this way,

you create a feedback

loop, and the current that

you measure through the

CCCS is the input-offset

current. The feedback

loop implements a high

gain that ensures a high

accuracy (negligible error

140

rent of a current mirror is straight-

forward. You simply have to apply an

input current, measure the output cur-

rent, and calculate the difference. This

output-offset current, however, is not

equal to the input-offset current, espe-

cially when the circuit is not a 1-to-1 mir-

ror. Simulating the input-offset current

with high accuracy is more complicated.

Suppose you’re dealing with a 1-to-1 mir-

ror and you want to know what input

current is needed to obtain an output

current of 10

120

100

A. Ideally, the input cur-

rent would be 10

–300 –200 –100 0 100 200 300 400 500 600 700

INPUT-OFFSET CURRENT (nA)

A, assuming that the

input offset current is zero. However, be-

cause of the finite beta of bipolar tran-

sistors, finite output impedances, mis-

Figure 2

This bar graph shows the input offset-current distribution.

current). And, because you obtain the re-

sult by calculating the dc operating

point, the simulation time is small.

Figure 2 shows simulation results of

500 Monte Carlo runs for I IDEAL

CCCS

G*I ERROR

I IDEAL

1V. The npn

transistors have an emitter length of 40

microns and use a 0.35-micron silicon-

germanium BiCMOS process, but you

can use the simulation method for all

current mirrors and all types of transis-

tors. The average of the distribution in

Figure 2 is 194 nA, and the standard de-

viation is 131 nA. The average is not zero

because of the base-current error.

1000, and V OUT

I ERROR

V OUT

Figure 1

Use this circuit for simulation of current-mirror input-offset currents.

Designing high-current chokes is easy

Louis Vlemincq, Belgacom, Evere, Belgium

Idea deals with a formula rather

than a circuit. You might think that

all the basic formulas of magnetic phe-

nomena were discovered more than a

century ago. In fact, they probably were,

but, at the time, some were of little prac-

tical interest and were essentially disre-

garded and never included in books or

formula tables. I developed the formu-

la describe here because I had to design

many inductive components subjected

to high peak currents, such as dc filter

chokes, ac reactors for resonant con-

verters, and flyback transformers. In

such cases, you have to consider two

main aspects: One is the current-carry-

ing capacity of the wire, and the other is

the peak induction that the core mate-

rial supports. The first point is well-

known and relatively easy to deal with,

but the magnetic induction is much

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