Digital Filter Design And Synthesis Using High Level Modeling Tools.pdf

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DIGITAL FILTER DESIGN AND SYNTHESIS USING HIGH-LEVEL MODELING TOOLS
by
Brian A. Jackson
Thesis submitted to the Faculty of
Virginia Polytechnic Institute and State University
in partial fulfillment of the requirements for the degree of
Masters of Science
in
Electrical Engineering
Dr. James R. Armstrong, Thesis Advisor
Dr. F. Gail Gray
Dr. Dong S. Ha
Wednesday, December 1, 1999
Blacksburg, Virginia
Keywords: VHDL, COSSAP, MATLAB, digital filters
DIGITAL FILTER DESIGN AND SYNTHESIS USING HIGH-LEVEL MODELING TOOLS
by
Brian A. Jackson
Dr. James R. Armstrong, Thesis Advisor
Virginia Polytechnic Institute and State University
The Bradley Department of Electrical and Computer Engineering
ABSTRACT
The purpose of this thesis is to formulate a technically sound approach to designing Infinite Impulse
Response (IIR) digital filters using high-level modeling tools. High-level modeling tools provide the ability
to build and simulate ideal models. Once proper validation is complete on these ideal models, the user
can then migrate to lower levels of abstraction until an actual real world model is designed. High-level
modeling tools are the epitome of the top-down design concept in which design first takes place with the
basic functional knowledge of a system. With each level of abstraction, validation is performed. High-level
modeling tools are used throughout industry and their application is continually growing especially in the
DSP area where many modes of communications are expanding. High-level modeling tools and validation
significantly address this complex expansion by utilizing an ideal representation of a complicated network.
ii
TABLE OF CONTENTS
Abstract............................................................................................................................................. ii
Table of Contents ............................................................................................................................ iii
Chapter 1: Introduction .....................................................................................................................1
Chapter 2: Quantization....................................................................................................................3
2.1: Quantization ..............................................................................................................................3
2.2: Quantization Noise ....................................................................................................................3
2.3: Two’s Complement Representation ..........................................................................................3
2.4: Two’s Complement Truncation..................................................................................................3
2.5: Two’s Complement Rounding ...................................................................................................4
2.6: Finite-Precision Effects..............................................................................................................4
2.7: Limit-Cycle Oscillations .............................................................................................................5
Chapter 3: IIR Digital Filter Structures..............................................................................................7
3.1: Linear Time-Invariant Systems..................................................................................................7
3.2: Difference equations and Recursive Systems ..........................................................................7
3.3: Infinite Impulse Response (IIR) Digital Filters ...........................................................................8
3.4: Hardware Consideration..........................................................................................................10
3.4.1: Parallel-Form Structure ........................................................................................................10
3.4.2: Cascade-Form Structure ......................................................................................................12
Chapter 4: Digital Filter Designs.....................................................................................................14
Chapter 5: COSSAP Saturation Modes for Fixed-point Binary Adders .........................................16
5.1: Overflow in Binary Addition .....................................................................................................16
5.2: COSSAP Saturation Modes ....................................................................................................16
Chapter 6: COSSAP Round-off Modes for Fixed-point Binary Multipliers .....................................20
Chapter 7: Editing VHDL-dumped Code Produced from COSSAP ...............................................25
7.1: Designing IIR Filters in COSSAP Block Diagram Editor .........................................................25
7.2: Deficiencies in the VHDL code generated by xvcg ................................................................27
7.2.1: Fixed-point Multiplier Sub-blocks .........................................................................................27
7.2.2: Fixed-point Adder Sub-blocks ..............................................................................................27
7.2.3: Fixed-point Delay Sub-blocks...............................................................................................29
7.3: Designing IIR Filters in VHDL..................................................................................................29
Chapter 8: Digital Filter Design Procedures Using High-level Tools..............................................31
8.1: IIR Digital Filter Design Flowchart ...........................................................................................31
8.2: Description of Flowchart Steps................................................................................................33
Chapter 9: Results of IIR Digital Filter Design Methodology ..........................................................40
9.1: 16-bit Butterworth Lowpass Filter Design................................................................................40
9.1.1: Parallel Structure Implementation of Butterworth Lowpass Filter ........................................43
9.1.1.1: Results of Validation Test #1.............................................................................................57
9.1.1.2: Results of Validation Test #2.............................................................................................61
9.1.2: Cascade Structure Implementation of Butterworth Lowpass Filter ......................................66
9.1.2.1: Results of Validation Test #1.............................................................................................73
9.1.2.2: Results of Validation Test #2.............................................................................................74
9.1.3: VHDL Synthesis of Parallel Structure...................................................................................78
9.1.4: VHDL Synthesis of Cascade Structure ................................................................................79
Chapter 10: Results of Design Methodology for DSP Applications ...............................................80
iii
10.1: Voice Communication Bandwidth Results ............................................................................80
10.1.1: Parallel Structure of Butterworth Bandpass Filter Results .................................................84
10.1.1.1: Results of Validation Test #1...........................................................................................92
10.1.1.2: Results of Validation Test #2...........................................................................................93
10.1.2: Cascade Structure of Butterworth Bandpass Filter Results ...............................................97
10.1.2.1: Results of Validation Test #1.........................................................................................105
10.1.2.2: Results of Validation Test #2.........................................................................................106
10.2: Digital Video Bandwidth Results .........................................................................................109
10.2.1: Parallel Structure of Chebyshev Type II Lowpass Filter Results .....................................112
10.2.1.1: Results of Validation Test #1.........................................................................................119
10.2.1.2: Results of Validation Test #2.........................................................................................120
10.2.2: Cascade Structure of Chebyshev Type II Lowpass Filter Results ...................................124
10.2.2.1: Results of Validation Test #1.........................................................................................132
10.2.2.2: Results of Validation Test #2.........................................................................................133
10.3: Data Communication and Imaging Bandwidth Results .......................................................136
10.3.1: Parallel Structure of Elliptic Bandpass Filter Results .......................................................139
10.3.2: Cascade Structure of Elliptic Bandpass Filter Results .....................................................142
10.3.2.1: Results of Validation Test #1.........................................................................................150
10.3.2.2: Results of Validation Test #2.........................................................................................151
Chapter 11: Research Summary and Future Work......................................................................156
Bibliography..................................................................................................................................157
Appendix A: Generic VHDL Library..............................................................................................158
Appendix B: Additional Results of 3 rd order 16-bit Lowpass Butterworth Filter............................166
Appendix C: Pole/Zero Plots of 3 rd order 16-bit Lowpass Chebyshev Type I Filter .....................181
Appendix D: Pole/Zero Plots of 3 rd order 16-bit Lowpass Chebyshev Type II Filter ....................184
Appendix E: Pole/Zero Plots of 3 rd order 16-bit Lowpass Elliptic Filter ........................................187
Appendix F: Synthesis-ready VHDL Library (8-bit and 16-bit examples).....................................190
Appendix G: Synthesis Script Files for Sub-blocks (16-bit example) ...........................................193
Acknowledgements ......................................................................................................................196
Vita................................................................................................................................................197
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CHAPTER 1: Introduction
The purpose of this thesis research is to formulate a technically sound approach to designing Infinite
Impulse Response (IIR) digital filters using high-level modeling tools. The basic functional need for
filtering is to pass a range of frequencies while rejecting others. This need for filtering has many technical
uses in the digital signal processing (DSP) areas of data communications, imaging, digital video, and
voice communications. Digital signal processing techniques are being used to handle these demanding
challenges in digital communications system design.
Analog filters are continuous-time systems for which both the input and output are continuous-time
signals. Digital filters are discrete-time systems whose input and output are discrete-time signals. Digital
filters are implemented using electronic digital circuits that perform the operations of delay, multiplication,
and addition. Analog filters are implemented using resistors, inductors, capacitors, and, possibly,
amplifiers [Chirlian]. The values of these analog components can drift over time and their precision is
limited. In addition, especially when filtering takes place at low frequencies, inductors are often large and
heavy. The multiplier coefficients of digital filters are established by the circuitry and do not drift. The
precision of the multiplier values can be made as large as desired by increasing the complexity of the
circuitry. Digital filters can be implemented using integrated circuits so that the per unit cost of digital filter
construction is less than a comparable analog filter [Chirlian]. Tolerances and accuracy considerations
are important factors for both analog and digital signal processing. Digital signal processing provides
better control of accuracy requirements. Wide tolerances in analog filters make it extremely difficult for a
system designer to control the accuracy of an analog signal processing system. A system designer has
much better control of accuracy of digital systems in terms of word length, floating-point versus fixed-point
arithmetic, and other similar factors [Manolakis]. These are the major advantages of digital filters.
High-level modeling tools provide the ability to build and simulate ideal models. Once proper validation is
complete on these ideal models, the user can then migrate to lower levels of abstraction until an actual
real world model is designed. High-level modeling tools are the epitome of the top-down design concept
in which design first takes place with the basic functional knowledge of a system. With each level of
abstraction, validation is performed. High-level modeling tools are just beginning to be used throughout
industry and their application is continually growing especially in the DSP area where many modes of
communications are expanding. High-level modeling tools and validation significantly address this
complex expansion by introducing an ideal representation of a complicated network.
A high-productivity environment is needed to support development from system definition and algorithm
development to implementation and verification. An important key element deals with high-level modeling
and analysis tool sets. Two prominent DSP tool sets of this nature are COSSAP and SPW. These tools
allow fast, natural expression of single clock, multi-rate, and asynchronous systems; provide extremely
fast high-level simulations; and provide full support for hardware and software implementation and
verification at any abstract level. Another important DSP tool used for computation and visualization is the
software package called MATLAB. This DSP tool is a prominent problem-solving application used in both
universities and industry.
Another important key element in the aforementioned high-productivity environment deals with the
already-established, industrial move to use hardware description languages to document, simulate, and
synthesize an electronic system. The two prominent hardware description languages (HDLs) are VHDL
and Verilog. Both languages have the necessary constructs to support the modeling, simulation, and
synthesis of complicated digital systems. In addition, the benefits of making design specifications more
technology-independent, automating low-level details, and improving design quality make VHDL and
Verilog important tools for design.
Interfacing the two aforementioned key elements (HDLs and high-level tools) has significant technical
rewards in industry. Specifically, two key elements that have established, feasible interface-capabilities
are COSSAP and VHDL. Both these tools are heavily used in both universities and industry. COSSAP
and VHDL are linked in that COSSAP contains an extensive DSP library written in VHDL. For high-level
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