PCB Design Rules.doc

SIGNAL INTEGRITY

In the realm of high-speed digital design, signal integrity has become a critical issue, and is posing increasing challenges to the design engineers. Many signal integrity problems are electromagnetic phenomena in nature and hence related to the EMI/EMC discussions in the previous sections of this blog. We will discuss what the typical signal integrity problems are, where they come from, why it is important to understand them and how we can analyze and solve these issues. Several software tools available at present for signal integrity analysis and current trends in this area will also be introduced.

The term Signal Integrity (SI) addresses two concerns in the electrical design aspects – the timing and the quality of the signal. Does the signal reach its destination when it is supposed to? And also, when it gets there, is it in good condition? The goal of signal integrity analysis is to ensure reliable high-speed data transmission. In a digital system, a signal is transmitted from one component to another in the form of logic 1 or 0, which is actually at certain reference voltage levels. At the input gate of a receiver, voltage above the reference value Vih is considered as logic high, while voltage below the reference value Vil is considered as logic low. Picture - 1 shows the ideal voltage waveform in the perfect logic world, whereas Picture - 2 shows how signal will look like in a real system. More complex data, composed of a string of
bit 1 and 0s, are actually continuous voltage waveforms. The receiving component needs to sample the waveform in order to obtain the binary encoded information. The data sampling process is usually triggered by the rising edge or the falling edge of a clock signal as shown in the Picture 3. It is clear from the diagram that the data must arrive at the receiving gate on time and settle down to a non-ambiguous logic state when the receiving component starts to latch in. Any delay of the data or distortion of the data waveform will result in a failure of the data transmission. Imagine if the signal waveform in Picture - 2 exhibits excessive ringing into the logic gray zone while the sampling occurs, then the logic level cannot be reliably detected.

Picture 1

Picture 2

Picture 3

Typical SI Problems

“Timing” is everything in a high-speed system. Signal timing depends on the delay caused by the physical length that the signal must propagate. It also depends on the shape of the waveform when the threshold is reached. Signal waveform distortions can be caused by different mechanisms. But there are three mostly concerned noise problems:

--> Reflection Noise
Due to impedance mismatch, stubs, vias and other interconnect discontinuities.

--> Crosstalk Noise
Due to electromagnetic coupling between signal traces and vias.

--> Power/Ground Noise
Due to parasitics of the power/ground delivery system during drivers’ simultaneous switching output (SSO). It is sometimes also called Ground Bounce, Delta-I Noise or Simultaneous Switching Noise (SSN).

Besides these three kinds of SI problems, there are other Electromagnetic Compatibility or Electromagnetic Interference (EMC/EMI) problems that may contribute to the signal waveform distortions. When SI problems happen and the system noise margin requirements are not satisfied – the input to a switching receiver makes an inflection below Vih minimum or above Vil maximum; the input to a quiet receiver rises above Vil maximum or falls below Vih minimum; power/ground voltage fluctuations disturb the data in the latch, then logic error, data drop, false switching, or even system failure may occur. These types of noise faults are extremely difficult to diagnose and solve after the system is built or prototyped. Understanding and solving these problems before they occur will eliminate having to deal with them further into the project cycle, and will in turn cut down the development cycle and reduce the cost. In the later part of this chapter, we will have further investigations on the physical behavior of these noise phenomena, their causes, their electrical models for analysis and simulation, and the ways to avoid them.

Where SI Problems Happen

Since the signals travel through all kinds of interconnections inside a system, any electrical impact happening at the source end, along the path, or at the receiving end, will have great effects on the signal timing and quality. In a typical digital system environment, signals originating from the off-chip drivers on the die (the chip) go through c4 or wire-bond connections to the chip package. The chip package could be single chip carrier or multi-chip module (MCM). Through the solder bumps of the chip package, signals go to the Printed Circuit Board (PCB) level. At this level, typical packaging structures include daughter card, motherboard or backplane. Then signals continue to go to another system component, such as an ASIC (Application Specific Integrated Circuit) chip, a memory module or a termination block. The chip
packages, printed circuit boards, as well as the cables and connecters, form the so-called ifferent levels of electronic packaging systems, as illustrated in below. In each level of the packaging structure, there are typical interconnects, such as metal traces, vias, and power/ground planes, which form electrical paths to conduct the signals. It is the packaging interconnection that ultimately influences the signal integrity of a system.


SI In Electronic Packaging

Technology trends toward higher speed and higher density devices have pushed the package performance to its limits. The clock rate of present personal computers is approaching gigahertz range. As signal risetime becomes less than 200ps, the significant frequency content of digital signals extends up to at least 10 GHz. This necessitates the fabrication of interconnects and packages to be capable of supporting very fast varying and broadband signals without degrading signal integrity to unacceptable levels. While the chip design and fabrication technology have undergone a tremendous evolution: gate lengths, having scaled from 50 μm in the 1960s to 0.18 μm today, are projected to reach 0.1 μm in the next few years; on-chip clock frequency is doubling every 18 months; and the intrinsic delay of the gate is decreasing exponentially with time to a few tens of pico-seconds. However, the package design has lagged considerably. With current technology, the package interconnection delay dominates the system timing budget and becomes the bottleneck of the high-speed system design. It is generally accepted today that package performance is one of the major limiting factors of the overall system performance.

Advances in high performance sub-micron microprocessors, the arrival of gigabit networks, and the need for broadband Internet access, necessitate the development of high performance packaging structures for reliable high-speed data transmission inside every electronics system. Signal integrity is one of the most important factors to be considered when designing these packages (chip carriers and PCBs) and integrating these packages together.

Basic PCB Layout Tutorial

The Schematic

Before you even begin to lay out your PCB, you MUST have a complete and accurate schematic diagram. Many people jump straight into the PCB design with nothing more than the circuit in their head, or the schematic drawn on loose post-it notes with no pin numbers and no order. This just isn’t good enough, if you don’t have an accurate schematic then your PCB will most likely end up a mess, and take you twice as long as it should.

“Garbage-in, garbage-out” is an often used quote, and it can apply equally well to PCB design. A PCB design is a manufactured version of your schematic, so it is natural for the PCB design to be influenced by the original schematic. If your schematic is neat, logical and clearly laid out, then it really does make your PCB design job a lot easier. Good practice will have signals flowing from inputs at the left to outputs on the right. With electrically important sections drawn correctly, the way the designer would like them to be laid out on the PCB. Like putting bypass capacitors next to the component they are meant for. Little notes on the schematic that aid in the layout
are very useful. For instance, “this pin requires a guard track to signal ground”, makes it clear to the person laying out the board what precautions must be taken. Even if it is you who designed the circuit and drew the schematic, notes not only remind yourself when it comes to laying out the board, but they are useful for people reviewing the design.

Your schematic really should be drawn with the PCB design in mind.

It is outside the scope of this article to go into details on good schematic design, as it would require a complete article in its own right.

Imperial and Metric


The first thing to know about PCB design is what measurement units are used and their common terminologies, as they can be awfully confusing!

As any long time PCB designer will tell you, you should always use imperial units (i.e. inches) when designing PCBs. This isn’t just for the sake of nostalgia, although that is a major reason! The majority of electronic components were (and still are) manufactured with imperial pin spacing. So this is no time to get stubborn and refuse to use anything but metric units, metric will make laying out of your board a lot harder and a lot easier. If you are young enough to have been raised in the metric age then you had better start learning what inches are all about and how to convert them.

An old saying for PCB design is “thou shall use thous”. A tad confusing until you know what a “thou” is.A “thou” is 1/1000th of an inch, and is universally used and recognised by PCB designers and manufacturers everywhere. So start practicing speaking in terms of “10 thou spacing” and “25 thou grid”, you’ll sound like a professional in no time!

Now that you understand what a thou is, we’ll throw another spanner in the works with the term “mil” (or “mils”). 1 “mil” is the same as 1 thou, and is NOT to be confused with the millimeter (mm), which is often spoken the same as “mil”. The term “mil” comes from 1 thou being equal to 1 mili inch. As a general rule avoid the use of “mil” and stick to “thou”, it’s less confusing when trying to explain PCB dimensions to those metricated non-PCB people.

Some PCB designers will tell you not to use metric millimeters for ANYTHING to do with a PCB design. In the practical world though, you’ll have to use both imperial inches (thous) and the metric millimeter (mm). So which units do you use for what? As a general rule, use thous for tracks, pads, spacings and grids, which are most of your basic “design and layout” requirements. Only use mm for “mechanical and manufacturing” type requirements like hole sizes and board dimensions.

You will find that many PCB manufacturers will follow these basic guidelines also, for when they ask you to provide details for a quote to manufacture your board. Most manufacturers use metric size drills, so specifying imperial size holes really is counterproductive and can be prone to errors. Just to confuse the issue even further, there are many components (new surface mount parts are an example) which have metric pin spacing and dimensions. So you’ll often have to design some component footprints using metric grids and pads. Many component datasheets will also have metric dimensions even though the spacing are designed to an imperial grid. If you see a “weird” metric dimension like 1.27mm in a component, you can be pretty sure it actually has a nice round imperial equivalent. In this case 1.27mm is 50 thou.

Yes, PCB design can be confusing!

So whatever it is you have to do in PCB design you’ll need to become an expert at imperial to metric conversion, and vice-versa. To make your life easier though, all the major PCB drafting packages have a single “hot key” to convert between imperial and metric units instantly (“Q” on Protel for instance). It will help you greatly if you memorise a few key conversions, like 100 thou (0.1 inch) = 2.54mm, and 200 thou (0.2 inch) = 5.08mm etc.

Values of 100 thou and above are very often expressed in inches instead of thous. So 0.2 inch is more commonly used than 200thou. 1 inch is also commonly known as 1 “pitch”. So it is common to hear the phrase “0.1 inch pitch”, or more simply “0.1 pitch” with the inches units being assumed. This is often used for pin spacing on components.

100 thou is a basic “reference point” for all aspects of PCB design, and a vast array of common component lead spacing are multiples or fractions of this basic unit. 50 and 200 thou are the most common. Along with the rest of the world, the IPC standards have all been metricated, and only occasionally refer to imperial units. This hasn’t really converted the PCB industry though. Old habits die hard, and imperial still reigns supreme in many areas of practical usage.

Working to Grids

The second major rule of PCB design, and the one most often missed by beginners, is to lay out your board on a fixed grid. This is called a “snap grid”, as your cursor, components and tracks will “snap” into fixed grid positions. Not just any size grid mind you, but a fairly coarse one. 100 thou is a standard placement grid for very basic through hole work, with 50 thou being a standard for general tracking work, like running tracks between throughhole pads. For even finer work you may use a 25 thou snap grid or even lower. Many designers will argue over
the merits of a 20 thou grid vs a 25 thou grid for instance. In practice, 25 thou is often more useful as it allows you to go exactly half way between 50 thou spaced pads.

Why is a coarse snap grid so important? It’s important because it will keep your components neat and symmetrical; aesthetically pleasing if you may. It’s not just for aesthetics though - it makes future editing,dragging, movement and alignment of your tracks, components and blocks of components easier as your layout grows in size and complexity.

A bad and amateurish PCB design is instantly recognisable, as many of the tracks will not line up exactly in the center of pads. Little bits of tracks will be “tacked” on to fill in gaps etc. This is the result of not using a snap grid effectively.

Good PCB layout practice would involve you starting out with a coarse grid like 50 thou and using a progressively finer snap grid if your design becomes “tight” on space. Drop to 25 thou and 10 thou for finer routing and placement when needed. This will do 99% of boards. Make sure the finer grid you choose is a nice even division of your standard 100 thou. This means 50, 25, 20, 10, or 5 thou. Don’t use anything else, you’ll regret it.

A good PCB package will have hotkeys or programmable macro keys to help you switch between different snap grid sizes instantly, as you will need to do this often. There are two types of grids in a PCB drafting package, a snap grid as discussed, and a “visible” grid. The visible grid is an optional on-screen grid of solid or dashed lines, or dots. This is displayed as a background behind your design and helps you greatly in lining up components and tracks. You can have the snap grid and visible grid set to different units (metric or imperial), and this is often very helpful. Many designers prefer a 100 thou visible grid and rarely vary from that.

Some programs also have what is called an “Electrical” grid. This grid is not visible, but it makes your cursor “snap” onto the center of electrical objects like tracks and pads, when your cursor gets close enough. This is extremely useful for manual routing, editing and moving objects.
One last type of grid is the “Component” grid. This works the same as the snap grid, but it’s for component movement only. This allows you to align components up to a different grid. Make sure you make it a multiple of your Snap grid.

When you start laying out your first board, snap grids can feel a bit “funny”, with your cursor only being able to be moved in steps. Unlike normal paint type packages which everyone is familiar with. But it’s easy to get used to, and your PCB designs will be one step closer to being neat and professional.

Working from the top

PCB design is always done looking from the top of your board, looking through the various layers as if they were transparent. This is how all the PCB packages work. The only time you will look at your board from the bottom is for manufacturing or checking purposes. This “through the board” method means that you will have to get used to reading text on the bottom layers as a mirror image, get used to it!

Tracks

There is no recommended standard for track sizes. What size track you use will depend upon (in order of importance) the electrical requirements of the design, the routing space and clearance you have available, and your own personal preference. Every design will have a different set of electrical requirements which can vary between tracks on the board. All but basic non-critical designs will require a mixture of track sizes. As a general rule though, the bigger the track width, the better. Bigger tracks have lower DC resistance, lower inductance, can be easier and cheaper for the manufacturer to etch, and are easier to inspect and rework.

The lower limit of your track width will depend upon the “track/space” resolution that your PCB manufacturer is capable of. For example, a manufacturer may quote a 10/8 track/space figure. This means that tracks can be no less than 10 thou wide, and the spacing between tracks (or pads, or any part of the copper) can be no less than 8 thou. The figures are almost always quoted in thou’s, with track width first and then spacing.

Real world typical figures are 10/10 and 8/8 for basic boards. The IPC standard recommends 4thou as being a lower limit. Once you get to 6thou tracks and below though, you are getting into the serious end of the business, and you should be consulting your board manufacturer first. The lower the track/space figure, the greater care the manufacturer has to take when aligning and etching the board. They will pass this cost onto you, so make sure that you don’t go any lower than you need to. As a guide, with “home made” PCB manufacturing processes like laser printed transparencies and pre-coated photo resist boards, it is possible to easily get 10/10 and even 8/8 spacing.

Just because a manufacturer can achieve a certain track/spacing, it is no reason to “push the limits” with your design. Use as big a track/spacing as possible unless your design parameters call for something smaller. As a start, you may like to use say 25 thou for signal tracks, 50 thou for power and ground tracks, and 10-15 thou for going between IC and component pads. Some designers though like the “look” of smaller signal tracks like 10 or 15 thou, while others like all of their tracks to be big and “chunky”. Good design practice is to keep tracks as big as possible, and then to change to a thinner track only when required to meet clearance requirements.

Changing your track from large to small and then back to large again is known as “necking”, or “necking down”. This is often required when you have to go between IC or component pads. This allows you to have nice big low impedance tracks, but still have the flexibility to route between tight spots.

In practice, your track width will be dictated by the current flowing through it, and the maximum temperature rise of the track you are willing to tolerate. Remember that every track will have a certain amount of resistance, sothe track will dissipate heat just like a resistor. The wider the track the lower the resistance. The thickness of the copper on your PCB will also play a part, as will any solder coating finish.

The thickness of the copper on the PCB is nominally specified in ounces per square foot, with 1oz copper being the most common. You can order other thicknesses like 0.5oz, 2oz and 4oz. The thicker copper layers are useful for high current, high reliability designs.

The calculations to figure out a required track width based on the current and the maximum temperature rise are a little complex. They can also be quite inaccurate, as the standard is based on a set of non-linear graphs based on measured data from around half a century ago. These are still reproduced in the IPC standard.

A handy track width calculator program can be found at www.ultracad.com/calc.htm, and gives results based on the IPC graphs.

As a rule of thumb, a 10degC temperature rise in your track is a nice safe limit to design around. A handy reference table has been included in this article to give you a list of track widths vs current for a 10degC rise. The DC resistance in milli ohms per inch is also shown. Of course, the bigger the track the better, so don’t just blindly stick to the table.

 

Considerations in Designing the Printed Circuit Boards of Embedded Switching Power Supplies

The importance of a good printed circuit board (PCB) layout in switching power supplies cannot e overstated. Developing the schematic and bdebugging the breadboard is a good start, but the final, critical challenge is to layout the PCB. Fortunately, understanding the phenomenon behind the operation of the typical switching power supply makes the effort much easier.

The primary rule for the designer is to be involved with every aspect of the design of the switching power supply, including the PCB. He or she is the only person who best understands the functional requirements of the power supply within the final product. In doing this, the power supply designer should never allow a PCB designer to use the auto-routing routines within the PCB layout program. The autorouter routine only strives to connect nodes that utilize the same signal as stated in the netlist. It disregards the length of the traces needed to accomplish this. The autorouter also considers all grounds the same signal and connects them together without consideration of the actual types of signals running through certain traces. For the power supply designer and the PCB designer to execute a good PCB layout, knowing the signals that flow between components is very important.

Appreciating the subtle “black magic” aspects to the PCB layout is essential to the success of the product. These layout factors can affect the performance of the switching power supply and can also affect the product’s ability to be released into the market. The aspects of the product’s operation that affect the printed circuit board design are: radiated electromagnetic interference (radiated EMI), conducted EMI, power supply stability, efficiency and operational longevity. The two forms of EMI are tested by regulatory approval bodies such as UL, IEC, and numerous other regulatory bodies throughout the world. The product must pass these stringent EMI tests before it can be sold into its respective market. The remaining factors affect the product's basic operation and customer satisfaction.

Current Loops

Switching power supplies have large current pulses with very sharp edges flowing within the power supply circuit. These large current pulses have the greatest effect on the creation of EMI, and should be the primary focus of the PCB designer. These currents flow in definable “loops” and the circuits carrying these currents should be laid-out first. The low-level control circuitry is then subsequently coupled into specific spots in the layout. These loops are diagrammed in picture below for the three major basic topologies of switching power supplies. All of the other topologies are variations of these three.

The loops shown in below can be listed in the order of their greatest affect on noise generation and operational performance:

1.      The power switch high current loop.

2.      The rectifier high current loop.

3. The input source loop.
4. The output load loop.

The input source and output load current loops are filtered by input and output EMI filters (not shown). Their currents are composed of largely DC current. The AC components of these currents are created by the power supply and should be kept to a minimum. These AC components are the elements that make-up conducted EMI. Any AC energy that is allowed to pass over a long enough length of a conductor, is radiated into the product’s environment.

The input and output loops are of secondary concern because the large AC pulses seen inside the supply are filtered by the input filter and output filter capacitors respectively. This makes their potential for creating high frequency noise problems less than the two AC loops. These loops should be analyzed later since they are directly measured by the regulatory agencies. The power switch and rectifier current loops are entirely AC, or more appropriately, pulsating DC. They ave trapezoidal current waveforms with high peak currents and very sharp edges (di/dt).

The Major Current Loops within Switching Power Supply Topologies

The power switch loop and the output rectifier loop(s) should be laid out so that the “loop” has a very small circumference and is composed of traces that are short in length and wide in width. First, the circumference of the loop controls the amount of RF energy that can be radiated at lower frequencies where a significant amount of conducted RF energy exists. By making the loop circumference as short as possible, one does not provide an efficient antenna for these lower noise frequencies. A typical power supply conducts noise frequency components that remain very high until about 100 times the switching frequency and then fall at a rate of between -20 to -40 dB per decade. The lower the frequency a loop is allowed to radiate, the more energy is allowed to escape into the environment. Secondly, the width of the traces used within the high current loops directly dictate the amount of voltage drop which will appear around the loop. This voltage drop, when created by high current, also creates RF radiation. The inductance and resistance exhibited by a trace is inversely proportional to its width. Inductance lowers the frequency response of a loop and therefore is a more efficient antenna at lower frequencies. So the loop traces should be as wide as possible. Wide traces also provide better heatsinking for the power switch and rectifier(s). An example of a layout for the power switch and rectifier loops in a buck converter is shown in below. Notice the very short distances between all members of the two main AC loops.




The output rectifier loop in transformer-isolated topologies have the same layout requirements as the input power switch loop. An example layout for the rectifier loop within a flyback converter can be seen below.


Paralleled Capacitors

Paralleling capacitors is a common technique for lowering the overall equivalent series resistance (ESR) and equivalent series inductance (ESL) of a filter capacitor. This allows the resulting filter capacitor to source or sink higher levels of ripple current with much less internal heating. Here, the PC board layout has a direct affect upon how much “sharing” occurs in the current and heating of the paralleled capacitors. The physical characteristics of the PCB layout between the other components in the loop and each capacitor must be as identical as possible. If the layout is not identical, the capacitor with the lower series trace impedance will see higher peak currents and become hotter (i2R). To promote this sharing, there should be a form of layout symmetry to both leads of the capacitors. Once again the traces between the components within the loop should be as short and wide as possible. Any parasitic impedance that is introduced by the layout effectively isolates the capacitor from the loop. This makes the high frequency current pulses seek other sources or sinks outside the loop. This creates more conducted EMI when the high current pulses are allowed to escape from the loop and enter the external circuitry. Examples of layouts for paralleled capacitors can be seen in below.



The grounds within a switching power supply are considered separately, even though they makeup one leg of the high current loops previously discussed. They are special in that they represent the lowest potential return path for the currents and the potential from which all other signals are measured. They have both DC and AC signals being conducted between various points in the physical ground system. There are sections of the ground system that should be considered separately from one another. If these grounds are interconnected improperly, the power supply can become unstable.

SATA Interface Layout Considerations

Correct separation of the signal and shield grounds is required to isolate the ESD energy. This separation is a physical gap between all the planes on a PCB with no traces crossing and is commonly referred to as a moat. The AC and signal grounds can be shorted together, but only after the main AC ground connection point. The following examples are from actual products designed to meet all international regulatory requirements.

Picture below is a portion of a PCI-X HBA with two SATA ports. Note the large moat between the chassis ground plane and the signal ground plane. These two planes are shorted together at a single point by a SMT zero Ohm resistor near the top PCI bracket mounting hole. This connection point is used because it is the closest to the PCI bracket mounting screw, which will have the lowest impedance to the Chassis AC ground connection. ESD energy on the SATA cable will seek the chassis ground connection rather than the highly inductive path through the zero Ohm resistor and the signal ground plane. Do not use a thermal relief on this mounting hole as it will raise the impedance of this connection.

Picture below shows identical moats cut through the power plane of the same HBA. This technique is used to completely isolate the chassis ground section of the PCB. ESD energy can easily jump between planes that are not adequately physically isolated. According to MIL-P-13949/4C for FR4 material, the average dielectric strength (perpendicular to laminations) is 750V per mil (.001”) minimum (29.25 KV per mm). This value should be de-rated at least 25 to 50% to allow for material tolerances.


Picture below shows a small section of the PCB isolated by a moat. As in the previous examples, this moat separates the shield and signal ground on an SATA port. The large hole at the bottom (labeled M4) is a mounting hole tied to a metal chassis. This product uses an ATX-type PC power supply equipped with a grounded AC receptacle. This means that this mounting hole has very low impedance to AC ground for conducting ESD energy. (Do not use a thermal relief on the chassis ground connection hole). The mounting hole has a SMT 0 Ohm resistor to connect the signal ground to the chassis ground at this one point, sometimes called a Mecca ground. The signal ground has no other connection for ESD energy to flow so the ESD energy is routed into the chassis, away from the SATA port IC.


Picture below is from a product that uses an ungrounded “floor wart” power supply that supplies regulated DC directly to the eSATA device. Notice that the shield and signal grounds are shorted together by a 0 Ohm SMT resistor on the far side of the power input connection, away from the SATA port.


In all the previous examples, the connections between the chassis ground and signal ground is facilitated by a zero Ohm SMT resistor. This component is used instead of a direct trace connection to ground for two reasons:

1.      The small amount of case inductance of the SMT package helps to filter the very fast rise-time ESD bursts

2.      The value of the SMT device can be changed for tuning the response time of this connection

Note: To raise the inductance of this connection, an actual bead inductor can be used instead of the zero Ohm resistor. This connection is also the point where EMI causing common mode current is shunted to ground. Be careful not to significantly raise the high frequency impedance of this connection as it will adversely effect EMI emissions. While using an actual resistor may improve ESD immunity, the impedance increase in the signal ground path would significantly increase EMI emissions.

Proper impedance control of the PCBs and the SATA connections will improve both EMI and ESD performance. Other parameters like the size, number and high frequency response of the signal ground connections, may be inversely related and must be balanced between effective EMI shielding and adequate ESD protection. These parameters are very dependent on the particular implementation.

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