TP3410.PDF

September 1994

TP3410 ISDN Basic Access

Echo-Cancelling 2B1Q U Transceiver

General Description

The TP3410 is a complete monolithic transceiver for ISDN

Basic Access data transmission at either end of the U inter-

face. Fully compatible with ANSI specification T1.601, it is

built on National's advanced double-metal CMOS process,

and requires only a single a 5V power supply. A total of

160 kbps full-duplex transmission on a single twisted-pair is

provided, with user-accessible channels including 2 `B'

channels, each at 64 kbps, 1 `D' channel at 16 kbps, and an

additional 4 kbps for loop maintenance. 12 kbps of band-

width is reserved for framing. 2B1Q Line coding is used, in

which pairs of binary bits are coded into 1 of 4 quantum

levels for transmission at 80k symbols/sec (hence 2 Binary/

1 Quaternary). To meet the very demanding specifications

for k 1 in 10e7 Bit Error Rate even on long loops with cross-

talk, the device includes 2 Adaptive Digital Signal Proces-

sors, 2 Digital Phase-locked Loops and a controller for auto-

matic activation.

The digital interface on the device can be programmed for

compatibility with either of two types of control interface for

chip control and access to all spare bits. In one mode a

Microwire serial control interface is used together with a

2B a D digital interface which is compatible with the Time-di-

vision Multiplexed format of PCM Combo devices and back-

planes. This mode allows independent time-slot assignment

for the 2 B channels and the D channel.

Alternatively, the GCI (General Circuit Interface) may be se-

lected, in which the 2B a D data is multiplexed together with

control, spare bits and loop maintenance data on 4 pins.

Features

Y 2 `B' a `D' channel 160 kbps transceiver for LT and NT

Y Meets ANSI T1.601 U.S. Standard

Y 2B1Q line coding with scrambler/descrambler

Y Range exceeds 18 kft of Ý 26 AWG

Y l 70 dB adaptive echo-cancellation and equalization

Y On-chip timing recovery, no precision external

components

Y Direct connection to small line transformer

Y Automatic activation controller

Y Selectable digital interface formats:

Ð TDM with time-slot assigner up to 64 slots, plus

MICROWIRE TM control interface

Ð GCI (General Circuit Interface), or

Ð IDL (Inter-chip Digital Link)

Y Backplane clock DPLL allows free-running XTAL

Y Elastic data buffers meet Q.502 wander/jitter for Slave-

slave mode on PBX Trunk Cards and DLC

Y EOC and spare bits access with automatic validation

Y Block error counter

Y 6 loopback test modes

Y Single a 5V supply, 325 mW active power

Y 20 mW idle mode with line signal ``wake-up'' detector

Applications

Y LT, NT-1, NT-2 Trunks, U-TE's, Regenerators etc.

Y Digital Loop Carrier

Y POTS Pair-Gain Systems

Y Easy Interface to:

Ð Line Card Backplanes

Ð ``S'' Interface Device

TP3420A

Combo É and TRI-STATE É are registered trademarks of National Semiconductor Corporation.

MICROWIRE TM is a trademark of National Semiconductor Corporation.

The General Circuit Interface (G.C.I.) is an interface specification of the Group-of-Four Euro-

pean Telecommunications Companies.

Ð Codec/Filter Combos

TP3054/7 and TP3075/6

Ð LAPD Processor

MC68302, HPC16400

Ð HDLC Controller

TP3451

Block Diagram

Note: Pin names show Microwire mode.

TL/H/9151±1

C 1995 National Semiconductor Corporation

TL/H/9151

RRD-B30M115/Printed in U. S. A.

Connection Diagrams

Pin Names for MICROWIRE Mode

Pin Names for GCI Mode

TL/H/9151±2

TL/H/9151±3

Top View

Order Number TP3410J

See NS Package Number J28A

Pin Descriptions

Description

Symbol

Description

No.

24 GNDA Negative power supply pins, which must

9 GNDD1 be connected together close to the de-

23 GNDD2 vice. All digital signals are referenced to

these pins, which are normally at the sys-

tem 0V (Ground) potential.

5 CC A Positive power supply input for the analog

sections, which must be a 5V g 5% and

must be directly connected to V CC D.

8 CC D Positive power supply input for the digital

section, which must be a 5V g 5% and

must be directly connected to V CC A.

21 MCLK/ The 15.36 MHz Master Clock input, which

XTAL requires either a parallel resonance crystal

to be tied between this pin and XTAL2, or

a CMOS logic level clock input from a sta-

ble source (a TTL Logic ``1'' level is not

suitable). This clock does not need to be

synchronized to the system clock (BCLK

and FS), see Section 5.1.

20 XTAL2 The output of the crystal oscillator, which

should be connected to one end of the

crystal, if used; otherwise this pin must be

left open-circuit. Not recommended to

drive additional logic.

10 TSr/ This pin has 2 functions : in LT mode it is

SCLK an open-drain n-channel TSr output, which

goes low only during the time-slots as-

signed to the B1 and B2 channels at the

Br pin in order to enable the TRI-STATE

control of the backplane line-driver. In NT

mode it is a full CMOS 15.36 MHz syn-

chronous clock output which is frequency-

locked to the received line signal (unlike

the XTAL pins it is not free-running).

No.

22 TSFS The Transmit Superframe Sync pin, which

indicates the start of each 12 ms transmit

superframe at the U Interface. In NT mode

this pin is always an output. In LT mode it

may be selected to be either an input or

CMOS output via Register CR2; when se-

lected as an output the signal is a square-

wave. Must be tied low if selected as input

yet not driven.

25 LSD/RSFS This pin is an open-drain n-channel Line

Signal Detector output, which is normally

high-impedance and pulls low only when

the device is powered down and an incom-

ing wake-up signal is detected from the

far-end. As an option this pin can be pro-

grammed to be an output indicating the

start of the received superframe at the U

interface; an external pull-up resistor is re-

quired.

The RSFS signal indicates the start of

each 12 ms receive superframe from the U

Interface and is available in NT and LT

modes. The Received Superframe Synch

clock output is accessible on pin 25 by

writing X'1C04 and X'100C (or X'100E)

during device initialization. See TP3410

users manual AN-913, Part II Section

4.18).

1Lo a Transmit 2B1Q signal differential outputs

4Lo b to the line transformer. When used with an

appropriate 1:1.5 step-up transformer and

the line coupling circuit recommended in

the Applications section, the line signal

conforms to the output specifications in

the ANSI standard.

Symbol

Pin Descriptions (Continued)

PIN DESCRIPTIONS SPECIFIC TO MICROWIRE MODE

ONLY (MW e 1)

Symbol

Description

No.

17 CCLK The Microwire control channel Clock input,

which may be asynchronous with BCLK.

27 CS The Chip Select input, which enables the

Control channel data to be shifted in and

out when pulled low. When high, this pin

inhibits the Control interface.

26 INT The Interrupt output, a latched open-drain

output signal which is normally high-im-

pedance, and goes low to indicate a

change of status of the loop transmission

system. This latch is cleared when the

Status Register is read by the microproc-

essor.

16 Dx When the D-port is enabled this pin is the

digital input for D channel data to be trans-

mitted to the line clocked by DCLK or

BCLK, see Register CR2. When the D-port

is disabled via CR2, this pin must be tied to

GND.

15 Dr When the D-port is enabled this pin is the

TRI-STATE output for D channel data to

be received from the line clocked by DCLK

or BCLK, see Register CR2.

14 DCLK When the D-port is enabled, in DSI Slave

or Master mode, this is a 16 kHz clock

CMOS output for D channel data. When

the D-port is disabled or not used, this pin

must be left open-circuit.

PIN DESCRIPTIONS SPECIFIC TO GCI MODE ONLY

(MW e 0)

Symbol

Description

No.

2 i a Receive 2B1Q signal differential inputs

3 i b from the line transformer. For normal full-

duplex operation, these pins should be

connected to the Lo g pins through the

recommended coupling circuit, as shown

in the Applicati ons section.

28 MW The Microwire/GCI Select pin, which must

be tied to V CC D to enable the Microwire

Interface with any of the data formats at

the Digital System Interface.

12 BCLK The Bit Clock pin, which determines the

data shift rate for `B' and `D' channel data

on the digital interface side of the device.

When Digital System Interface (DSI) Slave

mode is selected (see Digital Interfaces

section), BCLK is an input which may be

any multiple of 8 kHz from 256 kHz to

4.096 MHz. It need not be synchronous

with MCLK.

When DSI Master mode is selected, this

pin is a CMOS output clock at 256 kHz,

512 kHz, 1.536 MHz, 2.048 MHz or 2.56

MHz, depending on the selection in Com-

mand Register 1. It is synchronous with

the data on Bx and Br.

6 FSa In DSI Slave mode, this pin is the Transmit

Frame Sync pulse input, requiring a posi-

tive edge to indicate the start of the active

channel time for transmit B1 channel data

into Bx. In DSI Master mode, this pin is a

Frame Sync CMOS output pulse conform-

ing with the selected Digital Interface for-

mat.

7 FSb In DSI Slave mode, this pin is the Receive

Frame Sync pulse input, requiring a posi-

tive edge to indicate the start of the active

channel time of the device for receive B

channel data out from Br (see DSI Format

section). In DSI Master mode this pin is a

Frame Sync CMOS output pulse conform-

ing with the selected Digital Interface for-

mat.

13 Bx The digital input for B and, if selected, D

channel data to be transmitted to the line;

must be synchronous with BCLK.

11 Br The TRI-STATE output for B and, if select-

ed, D channel data received from the line;

it is synchronous with BCLK.

18 CI The Microwire control channel data input.

19 CO The Microwire control channel TRI-STATE

output for stat us information. When not

enabled by CS, this output is high-imped-

ance.

*Crystal specifications: 15.36 MHz g 50 ppm parallel resonant; R S s 20 X .

Load with 33 pF to GND each side ( a 7 pF due to pin capacitance).

Symbol

Description

No.

28 MW The Microwire/GCI select input, which

must be tied to GND to enable the GCI

mode at the Digital System Interface.

27 MO The GCI Master/Slave select input for the

clock direction. Connect this pin low to se-

lect BCLK and FSa as inputs i.e., GCI

Slave; Selection of LT or NT mode must

be made in register CR2. When MO is con-

nected high, NT Mode is automatically se-

lected, and BCLK, FSa and FSb are out-

puts, i.e., the GCI Master, see Section 8.

12 BCLK The Bit Clock pin, which controls the shift-

ing of data on the Bx and Br pins, at a rate

of 2 BCLK cycles per data bit. When GCI

Slave mode is selected (see Digital Inter-

faces section), BCLK is an input which

may be any multiple of 16 kHz from

512 kHz to 6.144 MHz. It need not be syn-

chronous with MCLK.

When GCI Master mode is selected, this

pin is a CMOS output clock at 512 kHz or

1.536 MHz, depending on the connection

of the S2/CLS pin. It is synchronous with

the data on Bx and Br.

Pin Descriptions (Continued)

Description

Symbol

Description

No.

13 Bx

No.

17 S2/CLS In GCI Slave mode (MO e 0):

19 S1

The digital input for multiplexed B, D and

control data clocked by BCLK at the rate

of 1 data bit per 2 BCLK cycles, and 32

data bits per 8 kHz frame defined by FSa.

(

input pins S2, S1 and S0 together pro-

vide a 3-bit binary-coded select port for

the GCI channel number; S2 is the msb.

These pins must be connected either to

V CC D or GND to select the 1-of-8 GCI

slots which are available if BCLK t 4.096

MHz is used.

In GCI Master mode (MO e 1)

S2/CLS is the GCI Clock Select input.

Connect this pin high to select BCLK e

1.536 MHz; connect CLS low to select

BCLK e 512 kHz. SO/FSb is a Frame

Sync CMOS output pulse which identifies

the B2 channel.

18 ES1 While in GCI mode, the ES1, ES2 pins are

16 ES2

11 Br

The open-drain n-channel output for multi-

plexed B, D and control data clocked by

BCLK at the rate of 1 data bit per 2 BCLK

cycles, and 32 data bits per 8 kHz frame

defined by FSa. A pull-up resistor is re-

quired to define the logical 1 state.

6 FSa

In GCI Slave mode (MO connected low),

this pin is the 8 kHz Frame Sync pulse in-

put, requiring a positive edge to indicate

the start of the GCI slot time for both

transmit and receive data at Bx and Br. In

GCI Master mode, this pin is the 8 kHz

Frame Sync CMOS output pulse.

(

local input pins. The status of the pins can

be accessed via the RXM56 register bits

5,6 corresponding to ES1, ES2.

15 LEC

Latched External Control output, which is

the output of a latched bit in the TXM56

Symbol

7 SO/FSb

Functional Description

1.1 Power-On Initialization

When power is first applied, power-on reset circuitry initializ-

es the TP3410 and puts it into the power-down state, in

which all the internal circuits including the Master oscillator

are inactive and in a low power state except for the Line-

Signal Detect circuit; the line outputs Lo a /Lo b are in a

high impedance state. All programmable registers and the

Activation Sequence Controller are reset.

All states in the Command Registers initialize as shown in

their respective code tables. The desired modes for all pro-

grammable functions may be selected by writing to these

registers via the control channel (Microwire or Monitor chan-

nel, as appropriate). Microwire is functional regardless of

whether the device is powered up or down, whereas the

GCI channel requires the BCLK to be running.

1.2 Power-Up/Power-Down Control

Before powering up the device, the Configuration Registers

should be programmed with the required modes.

In Microwire mode and GCI Slave mode, the device is pow-

ered up and the MCLK started by writing the PUP command,

as described in the Activation section. In GCI Master mode,

there are 2 methods of powering up the device: the Bx data

input can be pulled low (local power-up command) or the

10 kHz wake-up tone may be received from the far-end.

The power-down state may be re-entered by writing a Pow-

er-down command. In the power-down state, all pro-

grammed register data is retained. Also, if the loop had

been successfully activated and deactivated, the adaptive

circuits are ``frozen'' and the coefficients in the Digital Signal

Processors are stored to enable rapid reactivation (``warm-

start'').

1.3 Reset

A software reset command is provided to enable the clear-

ing of the Activation sequencer without disconnecting the

power supply to the device, see the Activation section.

2.0 TRANSMISSION SECTION

2.1 Line Coding And Frame Format

For both directions of transmission, 2B1Q coding is used, as

illustrated in Figure1. This coding rule requires that binary

data bits are grouped in pairs, and each pair is transmitted

as a symbol, the magnitude of which may be 1 out of 4

equally spaced voltage levels (a ``Quat''). There is no sym-

bol value at 0V in this code, the relative quat magnitudes

being g 1 (the ``inner'' levels) and g 3 (the ``outer'' levels).

No redundacy is included in this code, and in the limit there

is no bound to the RDS, although scrambling controls the

RDS in a practical sense ( RDS is the Running Digital Sum,

which is the algebraic summation of all symbol values in a

transmission session).

The frame format used in the TP3410 follows the ANSI

standard, shown in Table I. Each complete frame consists

of 120 quats, with a line bit rate of 80 kq/s, giving a frame

duration of 1.5 ms. A 9 quat syncword defines the framing

boundary. Furthermore, a ``superframe'' consisting of 8

frames is defined in order to provide sub-channels within the

spare bits M1 to M6. Inversion of the syncword defines the

superframe boundary. Prior to transmission, all data, with

the exception of the syncword, is scrambled using a self-

synchronizing scrambler to implement the specified 23rd-or-

der polynomial. Descrambling is included in the receiver.

First Bit Second Bit Quat Pulse Amplitude

(Sign) (Magnitude) (Note 1)

1 0 a 3 a 2.5V

1 1 a 1 a 0.83V

0 1 b 1 b 0.83V

0 0 b 3 b 2.5V

Note 1: For isolated pulses into a 135 X termination with recommended

transformer interface.

TL/H/9151±25

FIGURE 1. 2B1Q Line-Coding Rule

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