Motorola_M68000AD.pdf

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M68000UMAD/AD

Communications and Advanced

Consumer Technologies Group

M68000

Addendum to

M68000

User Manual

August 7, 1997

This addendum to the

, Revision 8, provides corrections to the original text as

well as additional information. This document and other information on this product is maintained on the World

Wide Web at http://www.motorola.com/68000.

M68000UM/AD User’s Manual

OVERVIEW

This manual includes hardware details and programming information for the MC68HC000, the MC68HC001,

the MC68EC000, and the MC68SEC000. For ease of reading, the name M68000 MPUs will be used when

referring to all processors. Refer to M68000PM/AD,

M68000 Programmer's Reference Manual

, for detailed

information on the MC68000 instruction set.

The four microprocessors are very similar to each other and all contain the following features:

•

Sixteen 32-Bit Data and Address Registers

•

16-Mbyte Direct Addressing Range

•

Program Counter

•

6 Instruction Types

•

Operations on Five Main Data Types

•

Memory-Mapped Input/Output (I/O)

•

14 Addressing Modes

The following processors contain additional features:

•

MC68HC001/MC68EC000/MC68SEC000

—

Statically selectable 8- or 16-bit data bus

•

MC68HC000/MC68EC000/MC68HC001/MC68SEC000

—

Low power

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

SEMICONDUCTOR PRODUCT INFORMATION

1997 Motorola, Inc.

The primary features of the MC68SEC000 embedded processor include the following:

•

Direct Replacement for the MC68EC000

—

Pin-for-pin compatibility with the MC68EC000 in the plastic QFP and TQFP packages

—

Vast selection of existing third-party development tools for the MC68EC000 support the

MC68SEC000

—

Software written for the MC68EC000 will run unchanged on the MC68SEC000

•

Power Management

—

Low-power HCMOS technology

—

Static design allows for stopping the processor clock

—

3.3V or 5V operation

—

Typical 0.5

A current consumption at 3.3V in sleep mode

•

Software Strength

—

Fully upward object-code compatible with other M68000 Family products

—

M68000 architecture allows effective assembly code with a C compiler

•

Upgrade

—

Fully upward code-compatible with higher performance 680x0 and 68300 Family members

—

ColdFire

code-compatible with minor modifications

1. MC68HC000

The primary benefit of the MC68HC000 is reduced power consumption. The device dissipates less power (by

an order of magnitude) than the NMOS MC68000.

The MC68HC000 is an implementation of the M68000 16/-32 bit microprocessor architecture. The

MC68HC000 has a 16-bit data bus implementation of the MC68000 and is upward code-compatible with the

MC68010 and the MC68020 32-bit implementation of the architecture.

1.1 MC68HC001

The MC68HC001 provides a functional extension to the MC68HC000 HCMOS 16-/32-bit microprocessor with

the addition of statically selectable 8- or 16-bit data bus operation. The MC68HC001 is object-code compatible

with the MC68HC000. You can migrate code written for the MC68HC001 without modification to any member

of the M68000 Family.

1.2 MC68EC000

The MC68EC000 is an economical high-performance embedded controller designed to suit the needs of the

cost-sensitive embedded-controller market. The HCMOS MC68EC000 has an internal 32-bit architecture that

is supported by a statically selectable 8- or 16-bit data bus. This architecture provides a fast and efficient

processing device that can satisfy the requirements of sophisticated applications based on high-level

languages.

The MC68EC000 is fully object-code compatible with the MC68000. You can migrate code written for the

MC68EC000 without modification to any member of the M68000 Family.

The MC68EC000 brings the performance level of the M68000 Family to cost levels previously associated with

8-bit microprocessors. The MC68EC000 benefits from the rich M68000 instruction set and its related high code

density with low memory bandwidth requirements.

M68000 USER’S MANUAL ADDENDUM

MOTOROLA

1.3 MC68SEC000

The MC68SEC000 is a cost-effective static embedded processor engineered for low-power applications. In

addition to providing the substantial cost and performance benefits of the MC68EC000, the low-power mode

of the MC68SEC000 provides significant advantages in power consumption and power management. The

typical current consumption of the MC68SEC000 is only 0.5

A in static standby mode and 15.0mA in normal

3.3V operation. The MC68SEC000 operates in either 3.3V or 5.0V systems. The remarkably low power

consumption, small footprint packages, and static implementation are combined in the MC68SEC000 for low-

power applications such as portable measuring equipment, electronic games, and battery-operated hand-held

consumer products.

The HCMOS MC68SEC000’s static architecture is a direct replacement for the MC68EC000, which offers the

lowest cost entry point to 32-bit processing. The internal 32-bit architecture provides fast and efficient

processing that satisfies the requirements of sophisticated applications based on high-level languages.

All of the existing third-party developer tools widely available for the MC68EC000 will directly support the

MC68SEC000. You can find detailed descriptions of these tools in the

High Performance Embedded Systems

Source Catalog

MOTOROLA

M68000 USER’S MANUAL ADDENDUM

2.0 SIGNAL DESCRIPTION

Change Figure 3-3 on Page 3-2.

V CC

GND

CLK

A23-A0

ADDRESS BUS

DATA BUS

D15-D0

A S

R/W

UDS

LDS

DTACK

FC0

FC1

FC2

PROCESSOR

STATUS

ASYNCHRONOUS

BUS CONTROL

MC68SEC000

BUS ARBITRATION

CONTROL

IPL0

IPL1

IPL2

AVEC

BERR

RESET

HALT

MODE

SYSTEM

CONTROL

INTERRUPT

CONTROL

Figure 1. Input and Output Signals (MC68EC000 and MC68SEC000)

2.1 Data Bus (D15-D0)

In Section 3.2 on page 3-4, replace “The MC68EC000 and MC68HC001 use D7-D0 in 8-bit mode, and D15-

D8 are undefined.” with “Using the MC68HC001, MC68EC000, and MC68SEC000 mode pin, you can

statically select either 8- or 16-bit modes for data transfer. The MC68EC000, MC68SEC000, and

MC68HC001 use D7-D0 in 8-bit mode. D15-D8 are undefined.”

2.2 Bus Arbitration Control

In Section 3.4 on page 3-5, the sentence “In the 48-pin version of the MC68008 and MC68EC000, no pin is

available for the bus grant acknowledge signal; this microprocessor uses a two-wire bus arbitration

scheme.” should read “In the 64-pin MC68EC000 and MC68SEC000, no pin is available for the bus grant

acknowledge signal. These microprocessors use a two-wire bus arbitration scheme.”

2.3 System Control

The Mode subsection heading of Section 3.6 on page 3-7 should read ‘‘Mode (MODE) (MC68HC001/

68EC000/68SEC000).’’

2.4 MC68SEC000 Low-Power Mode

Add the following to Sections 4 and 5, Bus Operation.

The MC68SEC000 has been redesigned to provide fully static- and low-power operation. This section

describes the recommended method for placing the MC68SEC000 into a low-power mode to reduce the

M68000 USER’S MANUAL ADDENDUM

MOTOROLA

power consumption to its quiescent value

while maintaining the internal state of the processor. The

low-power mode described below will be routinely tested as part of the MC68SEC000 test vectors provided

by Motorola.

To successfully enter the low-power mode, the MC68SEC000 must first be in the supervisor mode. A

recommended method for entering the low-power mode is to use the TRAP instruction, which causes the

processor to begin exception processing, thus entering the supervisor mode. External circuitry should

accomplish the following steps during the trap routine:

Externally detect a write to the low-power address. You select this address which can be any address

in the 16 Mbyte addressing ran ge of the MC68SEC000. A write to the low-power address can be

detected by polling A23–A0, R/W, and FC2–FC0. When the low-power address is detected, R/W is

a logic low, and the function codes have a five (101) on their output, the processor is writing to the

low-power address in supervisor mode and user-designed circuitry should assert the

ADDRESS_MATCH signal shown in Figure 2 and Figure 3 .

ADDRESS_MATCH

CPU_CLK

R ESTART

RESET

SYSTEM_CLK

Figure 2. MC68SEC000 Low-Power Circuitry for 16-Bit Data Bus

ADDRESS_MATCH

CPU_CLK

R ESTART

RESET

SYSTEM_CLK

Figure 3. MC68SEC000 Low-Power Circuitry for 8-Bit Data Bus

Execute the STOP instruction. The external circuitry shown in Figure 2 and Figure 3 will count the

number of bus cycles starting with the write to the low-power address and will stop the processor

clock on the first falling edge of the system clock after the bus cycle that reads the immediate data

of the STOP instruction. Figure 3 has one more flip-flop than Figure 2 because the MC68SEC000 in

The preliminary speciﬁcation for the MC68SEC000’s current drain while in the low-power mode is Idd < 2

A for 3.3V operation and

Idd < 5

A for 5.0V operation.

M68000 USER’S MANUAL ADDENDUM

MOTOROLA

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