LM565a.pdf

The Phase Locked Loop IC

as a Communication

System Building Block

National Semiconductor

Application Note 46

Thomas B. Mills

June 1971

INTRODUCTION

The phase locked loop has been found to be a useful ele-

ment in many types of communication systems. It is used in

two fundamentally different ways: (1) as a demodulator,

where it is used to follow phase or frequency modulation

and (2) to track a carrier or synchronizing signal which may

vary in frequency with time.

When operating as a demodulator, the phase locked loop

may be thought of as a matched filter operating as a coher-

ent detector. When used to track a carrier, it may be thought

of as a narrow-band filter for removing noise from a signal.

Recently, a phase locked loop has been built on a monolith-

ic integrated circuit, incorporating the basic elements neces-

sary for operation: a double balanced phase detector and a

highly linear voltage controlled oscillator, the frequency of

which can be varied with either a resistor or capacitor.

BASIC PHASE LOCK LOOP OPERATION

Figure 1 shows the basic blocks of a phase locked loop.

The input signal e i is a sinusoid of arbitrary frequency, while

the VCO output signal, e o , is a sinsuoid of the same fre-

quency as the input b ut of arbitrary phase. If

e i e 0

2 E i sin [ 0 o t a i 1 (t)]

(1)

It can be seen that the action of the VCO is that of an

integrator in the feedback loop when the phase locked loop

is considered in servo theory.

A better understanding of the operation of the loop may be

obtained by considering that initially, the loop is not in lock,

but that the frequency of the input signal e i and VCO e o are

very close in frequency. Under these conditions e d will be a

beat note, the frequency of which is equal to the frequency

difference of e o and e i . This signal is also applied to the

VCO input, since it is low enough to pass through the filter.

The instantaneous frequency of the VCO is therefore

changing and at some point in time, if the VCO frequency

equals the input frequency, lock will result. At this instant, e f

will assume a level sufficient to hold the VCO frequency in

lock with the input frequency. If the tuning of the VCO is

changed (such as by varying the value of the tuning capaci-

tor) the frequency output of the VCO will attempt to change;

however, this will result in an instantaneous change in

phase angle between e i and e o , resulting in a change in the

dc level of e d which will act to maintain frequency lock: no

average frequency change will result.

Similarly, if e i changes frequency, an instantaneous change

will result in a phase change between e i and e o and hence a

dc level change in e d . This level shift will change the fre-

quency of the VCO to maintain lock.

The amount of phase error resulting from a given frequency

shift can be found by knowing the ``dc'' loop gain of the

system. Considering the phase detector to have a transfer

function:

e o e 0

2E o cos [ 0 o t a i 2 (t) ]

(2)

the output of the multiplier (phase detector) is

e d e e i # e o

e 2E i E o sin [ 0 o t a i 1 (t)] # cos [ 0 o t a i 2 (t)]

e E i E o sin [ i 1 (t) b i 2 (t) ] a E i E o sin [ 2 0 o t a i 1 (t) a

i 2 (t)] (3)

the low pass filter of the loop removes the ac components

of the multiplier output; the dc term is seen to be a function

of the phase angle between the VCO and the input signal.

E d e K D ( i 1 b i 2 )

and the voltage controlled oscillator to have a transfer func-

tion:

i 2 e K o e f

(6)

or taking the Laplace transform

i 2 (s) e

K o e f

(7)

TL/H/7363±1

the phase of the VCO output will be proportional to the inte-

gral of the control voltage.

Combining these equations:

i 2 (s)

i 1 (s) e

FIGURE 1. Basic Phase Locked Loop

The output of the VCO is related to its input control voltage

K o K d F(s)

s a K o K D F(s)

(8)

i 2 (t) e K o e f

(4)

i 1 (s) b i 2 (s)

i 1 (s)

s a K o K D F(s)

(9)

for e f e 0, Let

i 2 e 0 i , then

i 2 (t) eW e f (t) dt

(5)

C 1995 National Semiconductor Corporation

TL/H/7363

RRD-B30M115/Printed in U. S. A.

Application of the final value theorem of Laplace transforms

yields

data modulation must be followed. The transfer function of

the filter is simply:

t x % i 1 (s) b i 2 (s) e lim

s x 0

s 2 i 1 (s)

s a K o K D F(s)

(10)

e f

e d e

1 a sR 1 C 1

(13)

With a step change in phase of the input Di 1 , the Laplace

transform of the input is

substitution into (8) results in

i 2 (s)

i 1 (s) e

K o K D / u 1

s 2 a s/ u 1 a K o K D / u 1

i 1 (s) e

Di 1

which gives i e (s) e i 1 (s) b i 2 (s)

(14)

u 1 e R 1 C 1

In terms of servo theory, the damping factor and natural

frequencies are

x % i e (t) e lim

x 0

s Di 1

s a K o K D F(s) e 0

(11)

the loop will eventually track out any change of input phase,

and there will be no phase error in the steady state solution.

If the input is a step in frequency, of magnitude D0 , the

change in input phase will be a ramp:

i 1 (s) e D0 /s 2

substitution of this value i , into (10) results in

lim

0 n e

K o K D

R 1 C 1

(

1/2

(15)

g e 1

(R 1 C 1 K o K D )

(

1/2

(16)

x % i e (t) e lim

s a K o K D F(s) e

K o K D F(o)

(12)

x 0

this result shows the resulting phase error is dependent on

the magnitude of the frequency step and the ``dc'' loop gain

K o K D , which is also called the velocity error coefficient K v .It

should be noted that the dimensions of K o K D are 1/sec.

This can also be seen by considering K D e volts/radian,

while K o e radians/sec/volt. The product is

volts

radian c

u 1 e R1C1

TL/H/7363±2

sec

this can be thought of as the ``dc'' loop gain. (Note that

additional dc gain between the phase detector and the volt-

age controlled oscillator will increase the loop gain and

hence reduce the steady state phase error resulting from a

change in frequency of the input).

THE LOOP FILTER

In working with phase locked loops, it is necessary to con-

sider not only the ``dc'' performance described above, but

the ``ac'' or transient performance which is governed by the

components of the loop filter placed between the phase

detector and the voltage controlled oscillator. In fact, it is

this loop filter that makes the phase locked loop so power-

ful: only a resistor and capacitor are all that is needed to

produce an arbitrarily narrow bandwidth at any selected

center frequency.

The simplest filter is a single capacitor, Figure2, and is used

for wide bandwith applications, such as where wideband

radians/sec

volt

TL/H/7363±3

FIGURE 2. Phase Locked Loop with Simple Filter

From this it can be seen that large time constants for R 1 C 1

or high loop gain will reduce the damping factor and hence

decrease stability. Therefore, if a narrow bandwidth is de-

sired, the damping factor will become very small and insta-

bility will result. It is not possible to adjust bandwidth, loop

gain, and damping independently with this simple filter.

lim

With the addition of a damping resistor R 2 as shown in Fig-

ure 3, it is possible to choose bandwidth, damping factor

and loop gain independently; the transfer function of this

filter is

e d

e f e

1 a s u 2

1 a s u 1

(17)

the loop transfer function becomes:

i 2 (s)

i z (s) e

K o K D (s u 2 a 1) ( u 1 a u 2 )

s 2 a s(1 a K o K d u 2 )/ u 1 a K o K D / u 1

(18)

the loop natural frequency is

K o K D

u 1

(

1/2

0 n e

(19)

TL/H/7363±6

FIGURE 4. Filter Time Constant vs Natural Frequency

while the damping factor becomes

g e

u 1 K o K D

(

1/2

1 a u 2 K o K D

(

(20)

0 n u 2

(21)

u 1 e R1C1

u 2 e R2C1

TL/H/7363±4

TL/H/7363±5

TL/H/7363±7

FIGURE 5. Damping Time Constant vs

Natural Frequency

DESIGN CONSIDERATIONS

Considering the above discussion, there are really two pri-

mary considerations in designing a phase locked loop. The

use to which the loop is to be put will affect the design

criterion of the loop components. The two primary factors to

consider are:

1. Loop gain. As pointed out previously, this affects the

phase error between the input signal and the voltage con-

trolled oscillator for a given frequency shift of the input

signal. It also determines the ``hold in range'' of the loop

providing no components of the loop go into limiting or

saturation. This is because the loop will remain in lock as

long as the phase difference between the input and the

VCO is less than g 90 § . The higher the loop gain, the

further the input can change in frequency before the 90 §

phase error is reached. The hold in range is

D0 H e g K o K D

FIGURE 3. Phase Locked Loop with

Damping Resistor Added

In practice, for a fixed loop gain K o K D , the natural frequency

of the loop may be chosen and will be dependent mainly on

u 1 , since u 2 m u 1 in most cases. Then, according to (21),

damping may be determined by u 2 and for all practical pur-

poses, will be an independent adjustment. These equations

are plotted in Figures4 and 5 and may be used for design

purposes.

(22)

(providing saturation or limiting does not occur).

2. Natural Frequency. The bandwidth of the loop is deter-

mined by the filter components R 1 ,R 2 and C 1 , and the

loop gain. Since the loop gain is normally selected by the

criterion in 1. above, the filter components are used to

select the bandwidth. The selection of loop bandwidth

may be governed by several things: noise bandwidth,

modulation rates if the loop is to be used as an FM de-

modulator, pull-in time and hold-in range. There are two

conflicting requirements that will have an affect on loop

bandwidth:

(a) Loop bandwidth must be as narrow as possible to

minimize output phase jitter due to external noise.

(b) The loop bandwidth should be made as large as pos-

sible to minimize transient error due to signal modula-

tion, output jitter due to internal oscillator (VCO) noise,

and to obtain best tracking and acquisition properties.

These two principles are in direct opposition and, depending

on what it is that the loop is to accomplish, an optimum

solution will lie somewhere between the two extremes.

If the phase locked loop is to be used to demodulate fre-

quency modulation, the design should proceed with the cri-

terion of b above. It is necessary to provide sufficient loop

bandwidth to accommodate the expected modulation. It

must be remembered that at all times, the loop must remain

in lock, (peak phase error less than 90 § ), even under ex-

tremes of modulation, such as peaks or step changes in

frequency.

For the case of sinusoidal frequency modulation, the peak

phase error as a function of frequency deviation and damp-

ing factor is shown in Figure6.

TL/H/7363±9

FIGURE 7. Transient Phase Error i e (t) Due to a

Step in Frequency D 0 . (Steady-State Velocity

Error, D0 /K v , Neglected)

TL/H/7363±10

TL/H/7363±8

FIGURE 8. Transient Phase Error i e (t) Due to a Ramp in

Frequency D 0 . (Steady-State Acceleration Error,

D0 / 0 n 2 , Included. Velocity Error, D0 t/K v , Neglected)

FIGURE 6. Steady-State Peak Phase Error Due to

Sinusoidal FM (High-Gain, Second-Order Loop)

It can be seen that the maximum phase error occurs when

the modulating frequency 0 m equals the loop natural fre-

quency 0 n ; if the loop has been designed with a damping

factor of 0.707, the peak phase error (in radians) will be 0.71

D 0 / 0 n ( D 0 e frequency deviation). From this plot, it is

possible to choose 0 n for a given deviation and modulation

frequency.

If the loop is to demodulate frequency shift keying (FSK), it

must follow step changes in frequency. The filter compo-

nents must then be chosen in accordance with the transient

phase error shown in Figure7. It must be remembered that

the loop filter must be wide enough so the loop will not lose

lock when a step change in frequency occurs: the greater

the frequency step, the wider the loop filter must be to main-

tain lock.

There is some frequency-step limit below which the loop

does not skip cycles, but remains in lock, called the ``pull-

out frequency'' 0 po . Viterbi has analyzed this and his results

are shown in Figure8, which plots normalized pull out fre-

quency for various damping factors for high gain second

order loops. Peak phase errors for other types of input sig-

nals are shown in Figures8 and 9.

TL/H/7363±11

FIGURE 9. Phase Error i e (t) Due to a Step in Phase Di

In designing loops to track a carrier or synchronizing signal,

it is desirable to make the loop bandwidth narrow so that

phase error due to external noise will be small. However, it

is necessary to make the loop bandwidth wide enough so

that any frequency jitter on the input signal will be followed.

NOISE PERFORMANCE

Since one of the main uses of phase locked loops is to

demodulate or track signals in noise, it is helpful to look at

how noise affects the operation of the phase locked loop.

The phase locked loop, as mentioned earlier, may be

thought of as a filter with a fixed, adjustable bandwidth. We

have seen how to calculate the loop natural frequency 0 n

(15), (19), and the damping factor g (16), (20). Without going

through a derivation, the loop noise bandwidth B L may be

shown to be

B L e

l H(j 0 ) l 2 df e 0 2

g a

4 g

(

Hz (23)

for a high gain, second order loop. This equation is plotted

inFigure10. It should be noted that the dimensions of noise

bandwidth are cycles per second while the dimensions of

0 n are radians per second.

TL/H/7363±13

FIGURE 11. Unlock Behavior of High-Gain,

Second-Order Loop, g e 0.707

When designing the loop filter components, enough band-

width in the loop must be allowed for instantaneous phase

change due to input noise. In the previous section, the filter

was selected on the basis that the peak error due to modu-

lation would be less than 90 § (so the loop would not loose

lock). However, if noise is present, the peak phase error will

increase due to the noise. So if the loop is not to lose lock

on these noise peaks the peak allowable error due to modu-

lation must be reduced to something less, on the order of

40 § to 50 § .

LOCKING

Initially, a loop is unlocked and the VCO is running at some

frequency. If a signal is applied to the input, locking may or

may not occur depending on several things.

If the signal is within the bandwidth of the loop filter, locking

will occur without a beat note being generated or any cycles

being skipped. This frequency is given by

TL/H/7363±12

FIGURE 10. Loop-Noise Bandwidth

(For High-Gain, Second-Order Loop)

Noise threshold is a difficult thing to analyze in a phase

locked loop, since we are talking about a statistical quantity.

Noise will show up in the input signal as both amplitude and

phase modulation. It can be shown that near optimum per-

formance of a phase locked loop can be obtained if a limiter

is used ahead of the phase detector, or if the phase detec-

tor is allowed to operate in limiting. With the use of a limiter,

amplitude modulation of the input signal by noise is re-

moved, and the noise appears as phase modulation. As the

input signal to noise ratio decreases, the phase jitter of the

input signal due to noise increases, and the probability of

losing lock due to instantaneous phase excersions will in-

crease. In practice it is nearly impossible to acquire lock if

the signal to noise ratio in the loop (SNR) L e 0 dB. In gen-

eral, (SNR) L of a 6 dB is needed for acquisition. If modula-

tion or transient phase error is present, a higher signal to

noise ratio is needed to acquire and hold lock.

A computer simulation performed by Sanneman and Row-

botham has shown the probability of skipping cycles for vari-

ous loop signal to noise ratios for high gain, second order

loops. Their data is shown in Figure11.

K o K D u 2

u 1 a u 2 & 2 g 0 n (24)

If the frequency of the input signal is further away from the

VCO frequency, locking may still occur, with a beat note

being generated. The greatest frequency that can be pulled

in is called the ``pull in frequency'' and is found from the

approximation

D0 P & 0

2 g 0 n K o K D b 0 n

1/2

(25)

which works well for moderate and high gain loops

( 0 n /K o K D k 0.4).

An approximate expression for pull in time (the time required

to achieve lock from some frequency offset D 0 ) is given by:

T P &

( D0 ) 2

2 g 0 n

A MONOLITHIC PHASE LOCKED LOOP

A complete phase locked loop has been built on a monolith-

ic integrated circuit. It features a very linear voltage con-

trolled oscillator and a double balanced phase detector.

D 0 L e

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