tl061-64.pdf

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LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
TL061, TL061A, TL061B, TL061Y, TL062, TL062A
TL062B, TL062Y, TL064, TL064A, TL064B, TL064Y
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078F – NOVEMBER 1978 – REVISED JANUARY 1999
Very Low Power Consumption
TL061, TL061A, TL061B
D, JG, P, OR PW PACKAGE
(TOP VIEW)
Typical Supply Current...200
m
A
(Per Amplifier)
Wide Common-Mode and Differential
Voltage Ranges
OFFSET N1
IN–
IN+
V CC–
1
2
3
4
8
7
6
5
NC
V CC+
OUT
OFFSET N2
Low Input Bias and Offset Currents
Common-Mode Input Voltage Range
Includes V CC+
TL061 ...U PACKAGE
(TOP VIEW)
Output Short-Circuit Protection
High Input Impedance...JFET-Input Stage
•
Internal Frequency Compensation
NC
OFFSET N1
IN–
IN+
V CC–
1
2
3
4
5
10
9
8
7
6
NC
NC
V CC+
OUT
OFFSET N2
Latch-Up-Free Operation
High Slew Rate...3.5 V/ m s Typ
description
The JFET-input operational amplifiers of the
TL06_ series are designed as low-power versions
of the TL08_ series amplifiers. They feature high
input impedance, wide bandwidth, high slew rate,
and low input offset and input bias currents. The
TL06_ series feature the same terminal
assignments as the TL07_ and TL08_ series.
Each of these JFET-input operational amplifiers
incorporates well-matched, high-voltage JFET
and bipolar transistors in a monolithic integrated
circuit.
TL062, TL062A, TL062B
D, JG, P, OR PW PACKAGE
(TOP VIEW)
1OUT
1IN–
1IN+
V CC–
1
2
3
4
8
7
6
5
V CC+
2OUT
2IN–
2IN+
TL062 ...U PACKAGE
(TOP VIEW)
The C-suffix devices are characterized for
operation from 0
NC
1OUT
1IN–
1IN+
V CC–
1
2
3
4
5
10
9
8
7
6
NC
V CC+
2OUT
2IN–
2IN+
C. The I-suffix devices
are characterized for operation from –40
C to 70
°
C to
C, and the M-suffix devices are characterized
for operation over the full military temperature
range of –55
C to 125
°
C.
TL064 . . . D, J, N, PW, OR W PACKAGE
TL064A, TL064B ...D OR N PACKAGE
(TOP VIEW)
1OUT
1IN–
1IN+
V CC+
2IN+
2IN–
2OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
4OUT
4IN–
4IN+
V CC–
3IN+
3IN–
3OUT
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright W 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
•
°
°
85
°
°
199644106.007.png 199644106.008.png 199644106.009.png
TL061, TL061A, TL061B, TL061Y, TL062, TL062A
TL062B, TL062Y, TL064, TL064A, TL064B, TL064Y
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
TL061 ...FK PACKAGE
(TOP VIEW)
TL062 . . . FK PACKAGE
(TOP VIEW)
TL064 . . . FK PACKAGE
(TOP VIEW)
NC
IN–
NC
IN+
NC
3212019
NC
V CC+
NC
OUT
NC
NC
1IN–
NC
1IN+
NC
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
NC
2OUT
NC
2IN–
NC
1IN+
NC
V CC+
NC
2IN+
3212019
18
17
16
15
14
4IN+
NC
V CC–
NC
3IN+
4
5
6
7
8
18
17
16
15
14
4
5
6
7
8
910111213
910111213
910111213
NC – No internal connection
AVAILABLE OPTIONS
PACKAGED DEVICES
T A
V IO MAX
AT 25 ° C
SMALL
OUTLINE
(D008) †
SMALL
OUTLINE
(D014) †
PLASTIC
DIP
(N)
PLASTIC
DIP
(P)
TSSOP
(PW)
CHIP FORM
(Y)
15 mV
6 mV
TL061CD
TL061ACD
TL061CD
TL061CP
TL061ACP
TL061CPW
TL061Y
3 mV
TL061BCD
TL061BCP
0
°
C
15 mV
6 mV
TL062CD
TL062CP
TL062CPW
TL062Y
to
TL062CD
TL062ACD
TL062CP
TL062ACP
TL062CPW
TL062Y
70
°
C
3 mV
TL062BCD
TL062BCP
15 mV
TL064CD
TL064CN
TL064CPW
TL064Y
6 mV
TL064ACD
TL064ACN
3 mV
TL064BCD
TL064BCN
PACKAGE
T A
V IO MAX
AT 25
°
C
SMALL
OUTLINE
(D008) †
SMALL
OUTLINE
(D014) †
CHIP
CARRIER
(FK)
CERAMIC
DIP
(J)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(N)
PLASTIC
DIP
(P)
FLAT
PACK
(U)
FLAT
PACK
(W)
40 C
to
TL061ID
TL062ID
TL061IP
TL062IP
6 mV
TL064ID
TL064IN
85 ° C
TL062ID
TL062IP
–55
°
C
6 mV
TL061MFK
TL061MJG
TL061MU
to
6 mV
TL062MFK
TL062MJG
TL062MU
125
°
C
9 mV
TL064MFK TL064MJ
TL064MW
† The D package is available taped and reeled. Add the suffix R to the device type (e.g., TL061CDR).
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SLOS078F – NOVEMBER 1978 – REVISED JANUARY 1999
15 mV
TL061CP
TL061CPW
TL061Y
15 mV
–40 ° C
TL061ID
TL061IP
•
199644106.010.png
TL061, TL061A, TL061B, TL061Y, TL062, TL062A
TL062B, TL062Y, TL064, TL064A, TL064B, TL064Y
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078F – NOVEMBER 1978 – REVISED JANUARY 1999
symbol (each amplifier)
IN+
+
OUT
–
IN–
OFFSET N1
Offset Null/Compensation
TL061 Only
OFFSET N2
schematic (each amplifier)
V CC+
IN+
IN–
50
W
100
W
C1
OFFSET N1
OFFSET N2
OUT
V CC–
TL061 Only
C1 = 10 pF on TL061, TL062, and TL064
Component values shown are nominal.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
199644106.001.png 199644106.002.png
TL061, TL061A, TL061B, TL061Y, TL062, TL062A
TL062B, TL062Y, TL064, TL064A, TL064B, TL064Y
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
TL061Y chip information
This chip, when properly assembled, has characteristics similar to the TL061. Thermal compression or
ultrasonic bonding can be used on the doped-aluminum bonding pads. The chips can be mounted with
conductive epoxy or a gold-silicon preform.
Bonding-Pad Assignments
(5)
(4)
(6)
(3)
OFFSET N1
(1)
V CC+
(7)
(3)
IN+
+
(6)
OUT
(2)
IN–
–
(7)
(5)
(4)
V CC–
41
OFFSET N2
Chip Thickness: 15 Mils Typical
Bonding Pads: 4
4 Mils Minimum
(1)
(2)
C
Tolerances Are
°
(8)
10%.
All Dimensions Are in Mils.
Pin (4) is Internally Connected
to Backside of Chip.
±
53
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SLOS078F – NOVEMBER 1978 – REVISED JANUARY 1999
×
T J (max) = 150
199644106.003.png 199644106.004.png
TL061, TL061A, TL061B, TL061Y, TL062, TL062A
TL062B, TL062Y, TL064, TL064A, TL064B, TL064Y
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078F – NOVEMBER 1978 – REVISED JANUARY 1999
TL062Y chip information
This chip, when properly assembled, has characteristics similar to the TL062. Thermal compression or
ultrasonic bonding can be used on the doped-aluminum bonding pads. The chips can be mounted with
conductive epoxy or a gold-silicon preform.
Bonding-Pad Assignments
(7)
(6)
(5)
(8)
(3)
V CC+
(8)
66
1IN+
+
(4)
(1)
1OUT
(2)
1IN–
–
(5)
+
(7)
2IN+
2OUT
(6)
–
2IN–
(4)
V CC–
Chip Thickness: 15 Mils Typical
Bonding Pads: 4
4 Mils Minimum
(1)
(2)
(3)
C
Tolerances Are
°
10%.
All Dimensions Are in Mils.
Pin (4) is Internally Connected to Backside of Chip.
±
49
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
×
T J (max) = 150
199644106.005.png 199644106.006.png

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