BUK555-100A-B_1.pdf

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Philips Semiconductors
Product Specification
PowerMOS transistor
BUK555-100A/B
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode
SYMBOL PARAMETER
MAX.
MAX.
UNIT
logic level field-effect power
transistor in a plastic envelope.
BUK555
-100A -100B
The device is intended for use in
V DS
Drain-source voltage
100
100
V
Switched Mode Power Supplies
I D
Drain current (DC)
25
22
A
(SMPS), motor control, welding,
P tot
Total power dissipation
125
125
W
DC/DC and AC/DC converters, and
T j
Junction temperature
175
175
˚C
in automotive and general purpose
R DS(ON)
Drain-source on-state
0.085
0.11
W
switching applications.
resistance;
V GS = 5 V
PINNING - TO220AB
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
tab
d
1
gate
2
drain
3
source
g
tab drain
123
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V DS
Drain-source voltage
-
-
100
V
V DGR
Drain-gate voltage
R GS = 20 k
W
-
100
V
±
V GS
Gate-source voltage
-
-
15
V
±
V GSM
Non-repetitive gate-source voltage t p
£
50
m
s
-
20
V
-100A
-100B
I D
Drain current (DC)
T mb = 25 ˚C
-
25
22
A
I D
Drain current (DC)
T mb = 100 ˚C
-
18
15
A
I DM
Drain current (pulse peak value)
T mb = 25 ˚C
-
100
88
A
P tot
Total power dissipation
T mb = 25 ˚C
-
125
W
T stg
Storage temperature
-
- 55
175
˚C
T j
Junction Temperature
-
-
175
˚C
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
R th j-mb
Thermal resistance junction to
-
-
1.2
K/W
mounting base
R th j-a
Thermal resistance junction to
-
60
-
K/W
ambient
April 1993
1
Rev 1.100
Logic level FET
22889814.009.png 22889814.010.png 22889814.011.png 22889814.012.png
Philips Semiconductors
Product Specification
PowerMOS transistor
BUK555-100A/B
STATIC CHARACTERISTICS
T mb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V (BR)DSS
Drain-source breakdown
V GS = 0 V; I D = 0.25 mA
100
-
-
V
voltage
V GS(TO)
Gate threshold voltage
V DS = V GS ; I D = 1 mA
1.0
1.5
2.0
V
I DSS
Zero gate voltage drain current V DS = 100 V; V GS = 0 V; T j = 25 ˚C
-
1
10
A
m
I DSS
Zero gate voltage drain current V DS = 100 V; V GS = 0 V; T j =125 ˚C
-
0.1
1.0
mA
I GSS
Gate source leakage current
V GS =
±
10 V; V DS = 0 V
-
10
100
nA
R DS(ON)
Drain-source on-state
V GS = 5 V;
BUK555-100A
-
0.075 0.085
W
resistance
I D = 13 A
BUK555-100B
-
0.09 0.11
W
DYNAMIC CHARACTERISTICS
T mb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
g fs
Forward transconductance
V DS = 25 V; I D = 13 A
10
13.5
-
S
C iss
Input capacitance
V GS = 0 V; V DS = 25 V; f = 1 MHz
-
1450 1750
pF
C oss
Output capacitance
-
280
350
pF
C rss
Feedback capacitance
-
100
150
pF
t d on
Turn-on delay time
V DD = 30 V; I D = 3 A;
-
25
40
ns
t r
Turn-on rise time
V GS = 5 V; R GS = 50
W
;
-
65
85
ns
t d off
Turn-off delay time
R gen = 50
W
-
135
180
ns
t f
Turn-off fall time
-
80
110
ns
L d
Internal drain inductance
Measured from contact screw on
-
3.5
-
nH
tab to centre of die
L d
Internal drain inductance
Measured from drain lead 6 mm
-
4.5
-
nH
from package to centre of die
L s
Internal source inductance
Measured from source lead 6 mm
-
7.5
-
nH
from package to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T mb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
I DR
Continuous reverse drain
-
-
-
25
A
current
I DRM
Pulsed reverse drain current
-
-
-
100
A
V SD
Diode forward voltage
I F = 25 A ; V GS = 0 V
-
1.3
1.7
V
t rr
Reverse recovery time
I F = 25 A; -dI F /dt = 100 A/
m
s;
-
90
-
ns
Q rr
Reverse recovery charge
V GS = 0 V; V R = 30 V
-
0.8
-
m
C
AVALANCHE LIMITING VALUE
T mb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
W DSS
Drain-source non-repetitive
I D = 25 A ; V DD
£
50 V ;
-
-
140
mJ
unclamped inductive turn-off
V GS = 5 V ; R GS = 50
W
energy
April 1993
2
Rev 1.100
Logic level FET
22889814.001.png
Philips Semiconductors
Product Specification
PowerMOS transistor
BUK555-100A/B
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
10
Zth j-mb / (K/W)
BUKx55-lv
1
D =
0.5
0.2
0.1
0.05
0.02
0.1
0.01
0
P
D
t p
D =
T
T
t
0.001
0
20 40 60 80 100 120 140 160 180
Tmb / C
1E-07
1E-05
1E-03
1E-01
1E+01
t / s
Fig.1. Normalised power dissipation.
PD% = 100
×
P D /P D 25 ˚C = f(T mb )
Fig.4. Transient thermal impedance.
Z th j-mb = f(t); parameter D = t p /T
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
Normalised Current Derating
ID / A
BUK555-100A
50
10
5
7
40
VGS / V =
4
30
20
3
10
0
20 40 60 80 100 120 140 160 180
Tmb / C
0
0
2
4
6
8
10
VDS / V
Fig.2. Normalised continuous drain current.
ID% = 100
I D /I D 25 ˚C = f(T mb ); conditions: V GS
³
5 V
Fig.5. Typical output characteristics, T j = 25 ˚C.
I D = f(V DS ); parameter V GS
1000
ID / A
BUK555-100A,B
RDS(ON) / Ohm
BUK555-100A
0.5
VGS / V =
0.4
2.5
3
3.5
A
100
B
tp = 10 us
0.3
4
100 us
0.2
4.5
10
DC
1 ms
10 ms
5
0.1
10
100 ms
1
1
10
100
1000
0
0
20
40
VDS / V
ID / A
Fig.3. Safe operating area. T mb = 25 ˚C
I D & I DM = f(V DS ); I DM single pulse; parameter t p
Fig.6. Typical on-state resistance, T j = 25 ˚C.
R DS(ON) = f(I D ); parameter V GS
April 1993
3
Rev 1.100
Logic level FET
t p
×
22889814.002.png 22889814.003.png 22889814.004.png
Philips Semiconductors
Product Specification
PowerMOS transistor
BUK555-100A/B
50
ID / A
BUK555-100A
VGS(TO) / V
Tj / C =
25
max.
150
2
40
30
typ.
min.
20
1
10
0
0
0
2
4
6
8
-60
-20
20
60
100
140
180
VGS / V
Tj / C
Fig.7. Typical transfer characteristics.
I D = f(V GS ) ; conditions: V DS = 25 V; parameter T j
Fig.10. Gate threshold voltage.
V GS(TO) = f(T j ); conditions: I D = 1 mA; V DS = V GS
gfs / S
BUK555-100A
ID / A
SUB-THRESHOLD CONDUCTION
20
1E-01
1E-02
15
1E-03
2 %
typ
98 %
10
1E-04
5
1E-05
0
1E-06
0
20
40
0
0.4
0.8
1.2
1.6
2
2.4
ID / A
VGS / V
Fig.8. Typical transconductance, T j = 25 ˚C.
g fs = f(I D ); conditions: V DS = 25 V
Fig.11. Sub-threshold drain current.
I D = f(V GS) ; conditions: T j = 25 ˚C; V DS = V GS
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
a
Normalised RDS(ON) = f(Tj)
10000
C / pF
BUK5y5-100
1000
Ciss
Coss
100
Crss
10
-60
-20
20
60
100
140
180
0
20
40
Tj / C
VDS / V
Fig.9. Normalised drain-source on-state resistance.
a = R DS(ON) /R DS(ON)25 ˚C = f(T j ); I D = 13 A; V GS = 5 V
Fig.12. Typical capacitances, C iss , C oss , C rss .
C = f(V DS ); conditions: V GS = 0 V; f = 1 MHz
April 1993
4
Rev 1.100
Logic level FET
22889814.005.png 22889814.006.png
Philips Semiconductors
Product Specification
PowerMOS transistor
BUK555-100A/B
12
VGS / V
BUK555-100
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
10
VDS / V =20
8
80
6
4
2
0
0
20
40
20
40
60
80
100 120 140 160 180
Tmb / C
QG / nC
Fig.13. Typical turn-on gate-charge characteristics.
V GS = f(Q G ); conditions: I D = 25 A; parameter V DS
Fig.15. Normalised avalanche energy rating.
W DSS % = f(T mb ); conditions: I D = 25 A
IF / A
BUK555-100A
50
+
VDD
40
L
VDS
30
-
VGS
-ID/10 0
20
T.U.T.
0
Tj / C = 150
25
10
RGS
R 01
shunt
0
0
1
2
VSDS / V
Fig.16. Avalanche energy test circuit.
Fig.14. Typical reverse diode current.
I F = f(V SDS ); conditions: V GS = 0 V; parameter T j
W DSS =
0.5
×
LI 2
×
BV DSS /(
BV DSS -
V DD )
April 1993
5
Rev 1.100
Logic level FET
22889814.007.png 22889814.008.png

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