24c16.pdf

ST24C16, ST25C16

ST24W16, ST25W16

SERIAL 16K (2K x 8) EEPROM

1 MILLION ERASE/WRITE CYCLES, with

40 YEARS DATA RETENTION

SINGLE SUPPLY VOLTAGE:

– 4.5V to 5.5V for ST24x16 versions

– 2.5V to 5.5V for ST25x16 versions

HARDWARE WRITE CONTROL VERSIONS:

ST24W16 and ST25W16

TWO WIRE SERIAL INTERFACE, FULLY I 2 C

BUS COMPATIBLE

BYTE and MULTIBYTE WRITE (up to 8

BYTES) for the ST24C16

PAGE WRITE (up to 16 BYTES)

BYTE, RANDOM and SEQUENTIAL READ

MODES

SELF TIMED PROGRAMING CYCLE

AUTOMATIC ADDRESS INCREMENTING

ENHANCED ESD/LATCH UP

PERFORMANCES

PSDIP8 (B)

0.25mm Frame

SO8 (M)

150mil Width

Figure 1. Logic Diagram

DESCRIPTION

This specification covers a range of 16K bits I 2 C

bus EEPROM products, the ST24/25C16 and the

ST24/25W16. In the text, products are referred to

as ST24/25x16 where "x" is: "C" for Standard ver-

sion and "W" for hardware Write Control version.

The ST24/25x16 are 16K bit electrically erasable

programmable memories (EEPROM), organized

as 8 blocks of 256 x 8 bits. These are manufactured

in SGS-THOMSON’s Hi-Endurance Advanced

CMOS technology which guarantees an endur-

V CC

PB0-PB1

SDA

PRE

ST24x16

ST25x16

SCL

Table 1. Signal Names

MODE/WC*

PRE

Write Protect Enable

PB0, PB1

Protect Block Select

SDA

Serial Data Address Input/Output

V SS

AI00866B

SCL

Serial Clock

MODE

Multybyte/Page Write Mode

(C version)

Write Control (W version)

V CC

Supply Voltage

V SS

Ground

Note: WC signal is only available for ST24/25W16 products.

March 1997

1/17

ST24/25C16, ST24/25W16

Figure 2A. DIP Pin Connections

Figure 2B. SO8 Pin Connections

ST24x16

ST25x16

ST24x16

ST25x16

PRE

V CC

PRE

V CC

PB0

MODE/WC

PB0

MODE/WC

PB1

SCL

PB1

SCL

V SS

SDA

V SS

SDA

AI00867B

AI00500B

Table 2. Absolute Maximum Ratings (1)

Symbol

Parameter

Value

Unit

T A

Ambient Operating Temperature

–40 to 125

T STG

Storage Temperature

–65 to 150

T LEAD

Lead Temperature, Soldering

(SO8)

(PSDIP8)

40 sec

10 sec

215

260

V IO

Input or Output Voltages

–0.6 to 6.5

V CC

Supply Voltage

–0.3 to 6.5

V ESD

Electrostatic Discharge Voltage (Human Body model) (2)

4000

500 V

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and

other relevant quality documents.

2. 100pF through 1500

Electrostatic Discharge Voltage (Machine model) (3)

; MIL-STD-883C, 3015.7

3. 200pF through 0

; EIAJ IC-121 (condition C)

DESCRIPTION (cont’d)

carry a built-in 4 bit, unique device identification

code (1010) corresponding to the I 2 C bus defini-

tion. The memories behave as slave devices in the

I 2 C protocol with all memory operations synchro-

nized by the serial clock. Read and write operations

are initiated by a START condition generated by the

bus master. The START condition is followed by a

stream of 4 bits (identification code 1010), 3 block

select bits, plus one read/write bit and terminated

by an acknowledge bit. When writing data to the

ance of one million erase/write cycles with a data

retention of 40 years. The ST25x16 operates with

a power supply value as low as 2.5V. Both Plastic

Dual-in-Line and Plastic Small Outline packages

are available.

The memories are compatible with the I 2 C stand-

ard, two wire serial interface which uses a bi-direc-

tional data bus and serial clock. The memories

2/17

ST24/25C16, ST24/25W16

Table 3. Device Select Code

Device Code

Memory MSB Addresses

Bit

Device Select

A10

Note: The MSB b7 is sent first.

Table 4. Operating Modes

Mode

RW bit

MODE pin

Bytes

Initial Sequence

Current Address Read

’1’

START, Device Select, RW = ’1’

Random Address Read

’0’

START, Device Select, RW = ’0’, Address,

’1’

reSTART, Device Select, RW = ’1’

Sequential Read

’1’

1 to 2048

As CURRENT or RANDOM Mode

Byte Write

’0’

START, Device Select, RW = ’0’

Multibyte Write

’0’

V IH

START, Device Select, RW = ’0’

Page Write

’0’

V IL

START, Device Select, RW = ’0’

Note: X = V IH or V IL .

memory it responds to the 8 bits received by as-

serting an acknowledge bit during the 9th bit time.

When data is read by the bus master, it acknow-

ledges the receipt of the data bytes in the same

way. Data transfers are terminated with a STOP

condition.

Data in the 4 upper blocks of the memory may be

write protected. The protected area is programma-

ble to start on any 16 byte boundary. The block in

which the protection starts is selected by the input

pins PB0, PB1. Protection is enabled by setting a

Protect Flag bit when the PRE input pin is driven

High.

Power On Reset: V CC lock out write protect. In

order to prevent data corruption and inadvertent

write operations during power up, a Power On

Reset (POR) circuit is implemented. Untill the V CC

voltage has reached the POR threshold value, the

internal reset is active: all operations are disabled

and the device will not respond to any command.

In the same way, when V CC drops down from the

operating voltage to below the POR threshold

value, all operations are disabled and the device

will not respond to any command. A stable V CC

must be applied before applying any logic signal.

3/17

ST24/25C16, ST24/25W16

SIGNALS DESCRIPTION

Serial Clock (SCL). The SCL input signal is used

to synchronise all data in and out of the memory. A

resistor can be connected from the SCL line to V CC

to act as a pull up (see Figure 3).

Serial Data (SDA). The SDA signal is bi-directional

and is used to transfer data in or out of the memory.

It is an open drain output that may be wire-OR’ed

with other open drain or open collector signals on

the bus. A resistor must be connected from the SDA

bus line to V CC to act as pull up (see Figure 3).

Protected Block Select (PB0, PB1). PB0 and PB1

input signals select the block in the upper part of

the memory where write protection starts. These

inputs have a CMOS compatible input level.

Protect Enable (PRE). The PRE input signal, in

addition to the status of the Block Address Pointer

bit (b2, location 7FFh as in Figure 7), sets the PRE

write protection active.

Mode (MO DE). The MODE input is available on pin

7 (see also WC feature) and may be driven dynami-

cally. It must be at V IL or V IH for the Byte Write

mode, V IH for Multibyte Write mode or V IL for Page

Write mode. When unconnected, the MODE input

is internally read as V IH (Multibyte Write mode).

Write Control (WC). An hardware Write Control

feature is offered only for ST24W16 and ST25W16

versions on pin 7. This feature is usefull to protect

the contents of the memory from any erroneous

erase/write cyc le. The Write Contro l sig nal is used

to enable (WC at V IH ) or disable (WC at V IL ) the

inter nal write protection. When unconnected, the

WC input is internally read as V IL . The devices with

this Write Control feature no longer supports the

Multibyte Write mode of operation, however all

other write modes are fully supported.

Refer to the AN404 Application Note for more de-

tailed information about Write Control feature.

Figure 3. Maximum R L Value versus Bus Capacitance (C BUS ) for an I 2 C Bus

V CC

R L

SDA

MASTER

SCL

C BUS

V CC = 5V

100

200

300

400

C BUS (pF)

AI01100

4/17

ST24/25C16, ST24/25W16

Table 5. Input Parameters (1) (T A = 25 ° C, f = 100 kHz )

Symbol

Parameter

Test Condition

Min

Max

Unit

C IN

Input Capacitance (SDA)

C IN

Input Capacitance (other pins)

Z WCL

WC Input Impedance (ST24/25W16)

V IN

0.3 V CC

Z WCH

WC Input Impedance (ST24/25W16)

V IN

0.7 V CC

500

t LP

Low-pass filter input time constant

(SDA and SCL)

100

Note: 1. Sampled only, not 100% tested.

Table 6. DC Characteristics

(T A = 0 to 70 ° C or –40 to 85 ° C; V CC = 4.5V to 5.5V or 2.5V to 5.5V)

Symbol

Parameter

Test Condition

Min

Max

Unit

I LI

Input Leakage Current

V IN

V CC

I LO

Output Leakage Current

V CC

SDA in Hi-Z

V OUT

I CC

Supply Current (ST24 series)

V CC = 5V, f C = 100kHz

(Rise/Fall time < 10ns)

Supply Current (ST25 series)

V CC = 2.5V, f C = 100kHz

Supply Current (Standby)

(ST24 series)

V IN = V SS or V CC ,

V CC = 5V

100

I CC1

V IN = V SS or V CC ,

V CC = 5V, f C = 100kHz

300

Supply Current (Standby)

(ST25 series)

V IN = V SS or V CC ,

V CC = 2.5V

I CC2

V IN = V SS or V CC ,

V CC = 2.5V, f C = 100kHz

V IL

Input Low Voltage (SCL, SDA)

–0.3

0.3 V CC

V IH

Input High Voltage (SCL, SDA)

0.7 V CC

V CC + 1

V IL

Input Low Voltage

(PB0 - PB1, PRE, MODE, WC)

–0.3

0.5

V IH

Input High Voltage

(PB0 - PB1, PRE, MODE, WC)

V CC – 0.5

V CC + 1

V OL

Output Low Voltage (ST24 series)

I OL = 3mA, V CC = 5V

0.4

Output Low Voltage (ST25 series)

I OL = 2.1mA, V CC = 2.5V

0.4

5/17

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