MC1496-D.PDF

MC1496, MC1496B

Balanced Modulators/

Demodulators

These devices were designed for use where the output voltage is a

product of an input voltage (signal) and a switching function (carrier).

Typical applications include suppressed carrier and amplitude

modulation, synchronous detection, FM detection, phase detection,

and chopper applications. See ON Semiconductor Application Note

AN531 for additional design information.

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SOIC−14

D SUFFIX

CASE 751A

Features

• Excellent Carrier Suppression −65 dB typ @ 0.5 MHz

−50 dB typ @ 10 MHz

• Adjustable Gain and Signal Handling

• Balanced Inputs and Outputs

• High Common Mode Rejection −85 dB Typical

• This Device Contains 8 Active Transistors

• Pb−Free Package is Available*

PDIP−14

P SUFFIX

CASE 646

PIN CONNECTIONS

Signal Input 1

V EE

N/C

Gain Adjust

Output

N/C

Carrier Input

Signal Input

Bias

Output

N/C

Input Carrier

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 12 of this data sheet.

DEVICE MARKING INFORMATION

See general marking information in the device marking

section on page 12 of this data sheet.

October, 2006 − Rev. 10

Publication Order Number:

MC1496/D

Gain Adjust

MC1496, MC1496B

I C = 500 kHz

I S = 1.0 kHz

I C = 500 kHz, I S = 1.0 kHz

499 kHz 500 kHz 501 kHz

Figure 1. Suppressed Carrier Output

Waveform

Figure 2. Suppressed Carrier Spectrum

8.0

I C = 500 kHz

I S = 1.0 kHz

6.0

4.0

2.0

I C = 500 kHz

I S = 1.0 kHz

499 kHz

500 kHz 501 kHz

Figure 3. Amplitude Modulation

Output Waveform

Figure 4. Amplitude−Modulation Spectrum

MAXIMUM RATINGS (T A = 25 ° C, unless otherwise noted.)

Rating

Symbol

Value

Unit

Applied Voltage

(V6−V8, V10−V1, V12−V8, V12−V10, V8−V4, V8−V1, V10−V4, V6−V10, V2−V5, V3−V5)

Vdc

Differential Input Signal

V8 − V10

V4 − V1

+5.0

± (5 + I5R e )

Vdc

Maximum Bias Current

I 5

Thermal Resistance, Junction−to−Air

Plastic Dual In−Line Package

100 ° C/W

Operating Ambient Temperature Range

MC1496

MC1496B

T A

0 to +70

−40 to +125

° C

Storage Temperature Range

T stg −65 to +150 ° C

Electrostatic Discharge Sensitivity (ESD)

Human Body Model (HBM)

Machine Model (MM)

ESD

2000

400

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

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MC1496, MC1496B

ELECTRICAL CHARACTERISTICS (V CC = 12 Vdc, V EE = −8.0 Vdc, I5 = 1.0 mAdc, R L = 3.9 k

, R e = 1.0 k

, T A = T low to T high ,

all input and output characteristics are single−ended, unless otherwise noted.) (Note 1 )

Characteristic

Fig.

Note

Symbol

Min

Typ

Max

Unit

Carrier Feedthrough

V C = 60 mVrms sine wave and

offset adjusted to zero

V C = 300 mVpp square wave:

offset adjusted to zero

offset not adjusted

V CFT

Vrms

f C = 1.0 kHz

f C = 10 MHz

−

140

−

mVrms

f C = 1.0 kHz

−

0.04

0.4

200

Carrier Suppression

f S = 10 kHz, 300 mVrms

f C = 500 kHz, 60 mVrms sine wave

f C = 10 MHz, 60 mVrms sine wave

V CS

−

Transadmittance Bandwidth (Magnitude) (R L = 50

)

BW 3dB

MHz

Carrier Input Port, V C = 60 mVrms sine wave

f S = 1.0 kHz, 300 mVrms sine wave

Signal Input Port, V S = 300 mVrms sine wave

|V C | = 0.5 Vdc

−

300

−

Signal Gain (V S = 100 mVrms, f = 1.0 kHz; | V C |= 0.5 Vdc)

A VS

2.5

3.5 − V/V

Single−Ended Input Impedance, Signal Port, f = 5.0 MHz

Parallel Input Resistance

Parallel Input Capacitance

6 −

r ip

c ip

−

200

2.0

−

Single−Ended Output Impedance, f = 10 MHz

Parallel Output Resistance

Parallel Output Capacitance

6 −

r op

c oo

−

5.0

−

Input Bias Current

7 −

I bS

;I bC

I10

I bS

I bC

−

Input Offset Current

I ioS = I1−I4; I ioC = I8−I10

7 − ⎥ I ioS ⎥

I ioC ⎥

−

0.7

7.0

Average Temperature Coefficient of Input Offset Current

(T A = −55 ° C to +125 ° C)

7 − ⎥ TC Iio ⎥ − 2.0 − nA/ ° C

Output Offset Current (I6−I9)

7 − ⎥ I oo ⎥ − 14

Average Temperature Coefficient of Output Offset Current

(T A = −55 ° C to +125 ° C)

7 − ⎥ TC Ioo ⎥ − 90 − nA/ ° C

Common−Mode Input Swing, Signal Port, f S = 1.0 kHz

CMV − 5.0 − Vpp

Common−Mode Gain, Signal Port, f S = 1.0 kHz, |V C |= 0.5 Vdc

9 − ACM − −85 − dB

Common−Mode Quiescent Output Voltage (Pin 6 or Pin 9)

10 − V out − 8.0 − Vpp

Differential Output Voltage Swing Capability

10 − V out − 8.0 − Vpp

Power Supply Current I6 +I12

Power Supply Current I14

I CC

I EE

−

2.0

3.0

4.0

5.0

mAdc

DC Power Dissipation

P D − 33 − mW

1. T low =0 ° C for MC1496

= −40 ° C for MC1496B

T high = +70 ° C for MC1496

= +125 ° C for MC1496B

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MC1496, MC1496B

GENERAL OPERATING INFORMATION

Carrier Feedthrough

Carrier feedthrough is defined as the output voltage at

carrier frequency with only the carrier applied

(signal voltage = 0).

Carrier null is achieved by balancing the currents in the

differential amplifier by means of a bias trim potentiometer

(R1 of Figure 5) .

Note that in the test circuit of Figure 10, V S corresponds to

a maximum value of 1.0 V peak.

Common Mode Swing

The common−mode swing is the voltage which may be

applied to both bases of the signal differential amplifier,

without saturating the current sources or without saturating

the differential amplifier itself by swinging it into the upper

switching devices. This swing is variable depending on the

particular circuit and biasing conditions chosen.

Carrier Suppression

Carrier suppression is defined as the ratio of each

sideband output to carrier output for the carrier and signal

voltage levels specified.

Carrier suppression is very dependent on carrier input

level, as shown in Figure 22. A low value of the carrier does

not fully switch the upper switching devices, and results in

lower signal gain, hence lower carrier suppression. A higher

than optimum carrier level results in unnecessary device and

circuit carrier feedthrough, which again degenerates the

suppression figure. The MC1496 has been characterized

with a 60 mVrms sinewave carrier input signal. This level

provides optimum carrier suppression at carrier frequencies

in the vicinity of 500 kHz, and is generally recommended for

balanced modulator applications.

Carrier feedthrough is independent of signal level, V S .

Thus carrier suppression can be maximized by operating

with large signal levels. However, a linear operating mode

must be maintained in the signal−input transistor pair −or

harmonics of the modulating signal will be generated and

appear in the device output as spurious sidebands of the

suppressed carrier. This requirement places an upper limit

on input−signal amplitude (see Figure 20 ). Note also that an

optimum carrier level is recommended in Figure 22 for good

carrier suppression and minimum spurious sideband

generation.

At higher frequencies circuit layout is very important in

order to minimize carrier feedthrough. Shielding may be

necessary in order to prevent capacitive coupling between

the carrier input leads and the output leads.

Power Dissipation

Power dissipation, P D , within the integrated circuit

package should be calculated as the summation of the

voltage−current products at each port, i.e. assuming

V12 = V6, I5 = I6 = I12 and ignoring base current,

P D = 2 I5 (V6 − V14) + I5)V5 − V14 where subscripts refer

to pin numbers.

Design Equations

The following is a partial list of design equations needed

to operate the circuit with other supply voltages and input

conditions.

A. Operating Current

The internal bias currents are set by the conditions at Pin 5.

Assume:

then :

I5 = I6 = I12,

I B

I C for all transistors

500

where: R5 is the resistor between

where: Pin 5 and ground

where:

= 0.75 at T A = +25 ° C

The MC1496 has been characterized for the condition

I 5 = 1.0 mA and is the generally recommended value.

B. Common−Mode Quiescent Output Voltage

V6 = V12 = V+ − I5 R L

Signal Gain and Maximum Input Level

Signal gain (single−ended) at low frequencies is defined

as the voltage gain,

Biasing

The MC1496 requires three dc bias voltage levels which

must be set externally. Guidelines for setting up these three

levels include maintaining at least 2.0 V collector−base bias

on all transistors while not exceeding the voltages given in

the absolute maximum rating table;

30 Vdc

A VS

V o

V S

R L

R e

where r e

26 mV

I5(mA)

[(V6, V12) − (V8, V10)]

2 Vdc

A constant dc potential is applied to the carrier input

terminals to fully switch two of the upper transistors “on”

and two transistors “off” (V C = 0.5 Vdc). This in effect

forms a cascode differential amplifier.

Linear operation requires that the signal input be below a

critical value determined by R E and the bias current I5.

V S

30 Vdc

[(V8, V10) − (V1, V4)]

2.7 Vdc

The foregoing conditions are based on the following

approximations:

V6 = V12, V8 = V10, V1 = V4

30 Vdc

[(V1, V4) − (V5)]

I5 R E (Volts peak)

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2r e

MC1496, MC1496B

Bias currents flowing into Pins 1, 4, 8 and 10 are transistor

base currents and can normally be neglected if external bias

dividers are designed to carry 1.0 mA or more.

Negative Supply

V EE should be dc only. The insertion of an RF choke in

series with V EE can enhance the stability of the internal

current sources.

Transadmittance Bandwidth

Carrier transadmittance bandwidth is the 3.0 dB bandwidth

of the device forward transadmittance as defined by:

Signal Port Stability

Under certain values of driving source impedance,

oscillation may occur. In this event, an RC suppression

network should be connected directly to each input using

short leads. This will reduce the Q of the source−tuned

circuits that cause the oscillation.

v s (signal) ⎥ V o 0

Signal transadmittance bandwidth is the 3.0 dB bandwidth

of the device forward transadmittance as defined by:

21C

i o (each sideband)

21S

v s (signal) ⎥ V c 0.5 Vdc, V o 0

i o (signal)

Signal Input

(Pins 1 and 4)

510

10 pF

Coupling and Bypass Capacitors

Capacitors C1 and C2 (Figure 5 ) should be selected for a

reactance of less than 5.0

at the carrier frequency.

An alternate method for low−frequency applications is to

insert a 1.0 k

Output Signal

The output signal is taken from Pins 6 and 12 either

balanced or single−ended. Figure 11 shows the output levels

of each of the two output sidebands resulting from variations

in both the carrier and modulating signal inputs with a

single−ended output connection.

resistor in series with the input (Pins 1, 4). In

this case input current drift may cause serious degradation

of carrier suppression.

TEST CIRCUITS

1.0 k

V CC

12 Vdc

R e = 1.0 k

R e

R L

3.9 k

R L

3.9 k

0.5 V

0.1 F

1.0 k

−

+V o

C 2

0.1

Carrier

Input V C

MC1496

Z out

Z in

−V o

+V o

MC1496

V S

−V o

Modulating

Signal Input

10 k

50 k

6.8 k

V I10 I5

−8.0 Vdc

V EE

6.8 k

−8.0 Vdc

Carrier Null

NOTE: Shielding of input and output leads may be needed

to properly perform these tests.

Figure 5. Carrier Rejection and Suppression

Figure 6. Input−Output Impedance

V CC

12 Vdc

1.0 k

V CC

12 Vdc

2.0 k

R e = 1.0 k

R e

1.0 k

0.1

1.0 k

0.01

Carrier

Input

V C

V S

2.0 k

50 50

0.1 F

+V o

−V o

MC1496

1.0 k

MC1496 6

Modulating

Signal Input

10 k

50 k

I10

6.8 k

V −

−8.0 Vdc

V EE

−8.0 Vdc

V EE

Carrier Null

Figure 7. Bias and Offset Currents

Figure 8. Transconductance Bandwidth

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