TDA2579B.PDF

INTEGRATED CIRCUITS

DATA SHEET

TDA2579B

Horizontal/vertical synchronization

circuit

Preliminary speciﬁcation

File under Integrated Circuits, IC02

September 1990

Philips Semiconductors

Preliminary speciﬁcation

Horizontal/vertical synchronization

circuit

TDA2579B

GENERAL DESCRIPTION

The TDA2579B generates and synchronizes horizontal and vertical signals. The device has a 3 level sandcastle output;

a transmitter identification signal and also 50/60 Hz identification.

Features

Horizontal phase detector, (sync to oscillator), sync separator and noise inverter

Triple current source in the phase detector with automatic selection

Second phase detector for storage compensation of the horizontal output

Stabilized direct starting of the horizontal oscillator and output stage from mains supply

Horizontal output pulse with constant duty cycle value of 29 m s

Internal vertical sync separator, and two integration selection times

Divider system with three different reset enable windows

Synchronization is set to 628 divider ratio when no vertical sync pulses and no video transmitter is identified

Vertical comparator with a low DC feedback signal

50/60 Hz identification output combined with mute function

Automatic amplitude adjustment for 50 and 60 Hz and blanking pulse duration

Automatic adaption of the burst-key pulsewidth

PACKAGE OUTLINE

18-lead dual in line; plastic (SOT 102); SOT102-1; 1996 November 19.

September 1990

Philips Semiconductors

Preliminary speciﬁcation

Horizontal/vertical synchronization circuit

TDA2579B

QUICK REFERENCE DATA

PARAMETER

CONDITION SYMBOL

MIN. TYP. MAX. UNIT

Supply

Minimum required current for starting

horizontal oscillator and output stage

I 16

6.2

Main supply voltage

V 10

Supply current

I 10

Input signals

Sync pulse input amplitude

V 5(p-p)

0.05

1.0

Horizontal ﬂyback pulse input current

I 12

Vertical comparator input signal

Voltage AC

V 2

0.8

Voltage DC

V 2

Output signals

Horizontal output (open collector)

I 11 =25mA

V 11

0.5

Vertical output stage driver

(emitter follower) I 1 = 1.5 mA

V 1

Sandcastle output levels

V 17 burst-key

V 17

9.8

horizontal blanking

V 17

4.5

vertical blanking

V 17

2.5

Video transmitter identiﬁcation output stage

(open collector loaded with external resistor to

positive supply). No sync. pulse present

V 13

0.5

I 13

Sync pulse present

divider ratio

576

V 13

V 10

divider ratio

576

V 13

7.65

September 1990

Philips Semiconductors

Preliminary speciﬁcation

Horizontal/vertical synchronization circuit

TDA2579B

September 1990

Philips Semiconductors

Preliminary speciﬁcation

Horizontal/vertical synchronization circuit

TDA2579B

FUNCTIONAL DESCRIPTION

Vertical part (pins 1,2,3,4)

The IC embodies a synchronized divider system for generating the vertical sawtooth at pin 3. The divider system has an

internal frequency doubling circuit, so the horizontal oscillator is working at its normal line frequency and one line period

equals 2 clock pulses. Due to the divider system no vertical frequency adjustment is needed. The divider has a

discriminator window for automatically switching over from the 60 Hz to 50 Hz system. The divider system operates with

3 different divider reset windows for maximum interference/disturbance protection.

The windows are activated via an up/down counter. The counter increases its counter value by 1 for each time the

separated vertical sync pulse is within the searched window. The count is decreased by 1 when the vertical sync pulse

is not present.

Large (search) window: divider ratio between 488 and 722

This mode is valid for the following conditions:

1. Divider is looking for a new transmitter.

2. Divider ratio found, not within the narrow window limits.

3. Up/down counter value of the divider system operating in the narrow window mode decreases below count 1.

4. Externally setting. This can be reached by loading pin 18 with a resistor of 220 k W to earth or connecting a 3.6 V

diode stabistor between pin 18 and ground.

Narrow window: divider ratio between 522-528 (60 Hz) or 622-628 (50 Hz).

The divider system switches over to this mode when the up/down counter has reached its maximum value of 12 approved

vertical sync pulses. When the divider operates in this mode and a vertical sync pulse is missing within the window the

divider is reset at the end of the window and the counter value is decreased by 1. At a counter value below count 1 the

divider system switches over to the large window mode.

Standard TV-norm

When the up/down counter has reached its maximum value of 12 in the narrow window mode, the information applied to

the up/down counter is changed such that the standard divider ratio value is tested. When the counter has reached a

value of 14 the divider system is changed over to the standard divider ratio mode. In this mode the divider is always reset

at the standard value even if the vertical sync pulse is missing. A missed vertical sync pulse decreases the counter value

by 1. When the counter reaches the value of 10 the divider system is switched over to the large window mode.

The standard TV-norm condition gives maximum protection for video recorders playing tapes with anti-copy guards.

No-TV-transmitter found: (pin 18

1.2 V)

In this condition, only noise is present, the divider is rest to count 628. In this way a stable picture display at normal height

is achieved.

Video tape recorders in feature mode

It should be noted that some VTRs operating in the feature modes, such as picture search, generate such distorted

pictures that the no-TV-transmitter detection circuit can be activated as pin V 18 drops below 1.2 V. This would imply a

rolling picture (see Phase detector, sub paragraph d). In general VTR-machines use a re-inserted vertical sync pulse in

the feature mode. Therefore the divider system has been made such that the automatic reset of the divider at count 628

when V 18 is below 1.2 V is inhibited when a vertical sync pulse is detected.

The divider system also generates the anti-top-flutter pulse which inhibits the Phase 1 detector during the vertical sync.

pulse. The width of this pulse depends on the divider mode. For the divider mode a the start is generated at the reset of

the divider. In mode b and c the anti-top-flutter pulse starts at the beginning of the first equalizing pulse.

September 1990

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