TDA8351.PDF

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Philips Semiconductors
Preliminary specification
DC-coupled vertical deflection circuit
TDA8351
FEATURES
·
Few external components
GENERAL DESCRIPTION
The TDA8351 is a power circuit for use in 90
°
and 110
°
·
Highly efficient fully DC-coupled vertical output bridge
circuit
colour deflection systems for field frequencies of 50 to
120 Hz. The circuit provides a DC driven vertical deflection
output circuit, operating as a highly efficient class G
system.
·
Vertical flyback switch
·
Guard circuit
·
Protection against:
– short-circuit of the output pins (7 and 4)
– short-circuit of the output pins to V P
·
Temperature (thermal) protection
·
High EMC immunity because of common mode inputs
·
A guard signal in zoom mode.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DC supply
V P
supply voltage
9
-
25
V
I q
quiescent supply current
-
30
-
mA
Vertical circuit
I O(p-p)
output current
(peak-to-peak value)
-
-
3
A
I diff(p-p)
differential input current
(peak-to-peak value)
-
600
-
m A
V diff(p-p)
differential input voltage
(peak-to-peak value)
-
1.5
1.8
V
Flyback switch
I M
peak output current
-
-
± 1.5
A
V FB
flyback supply voltage
-
-
50
V
note 1
-
-
60
V
Thermal data (in accordance with IEC 747-1)
T stg
storage temperature
- 55
-
+150
° C
T amb
operating ambient temperature
-
25
-
+75
°
C
T vj
virtual junction temperature
-
-
150
° C
Note
1. A flyback supply voltage of > 50 V up to 60 V is allowed in application. A 220 nF capacitor in series with a 22 W resistor
(dependent on I O and the inductance of the coil) has to be connected between pin 7 and ground. The decoupling
capacitor of V FB has to be connected between pin 6 and pin 3. This supply voltage line must have a resistance of
33 W (see application circuit Fig.6).
December 1994
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Philips Semiconductors
Preliminary specification
DC-coupled vertical deflection circuit
TDA8351
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
TDA8351
SIL9P
plastic single-in-line power package; 9 leads
SOT131-2
BLOCK DIAGRAM
handbook, full pagewidth
V P
V O(guard)
V FB
3
8
6
V P
CURRENT
SOURCE
TDA8351
V P
7
V O(A)
V O(A)
I S
I drive(pos)
1
I T
9
V I(fb)
I
T
I drive(neg)
2
V P
V
S
4
V O(B)
V O(B)
5
GND
MBC988- 1
Fig.1 Block diagram.
December 1994
3
I
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Philips Semiconductors
Preliminary specification
DC-coupled vertical deflection circuit
TDA8351
PINNING
FUNCTIONAL DESCRIPTION
The vertical driver circuit is a bridge configuration. The
deflection coil is connected between the output amplifiers,
which are driven in phase opposition. An external resistor
(R M ) connected in series with the deflection coil provides
internal feedback information. The differential input circuit
is voltage driven. The input circuit has been adapted to
enable it to be used with the TDA9150, TDA9151B,
TDA9160A, TDA9162, TDA8366 and TDA8376 which
deliver symmetrical current signals. An external resistor
(R CON ) connected between the differential input
determines the output current through the deflection coil.
The relationship between the differential input current and
the output current is defined by: I diff ´
SYMBOL
PIN
DESCRIPTION
I drive(pos)
1
input power-stage (positive);
includes I I(sb) signal bias
I drive(neg)
2
input power-stage (negative);
includes I I(sb) signal bias
V P
3
operating supply voltage
V O(B)
4
output voltage B
GND
5
ground
V FB
6
input flyback supply voltage
V O(A)
7
output voltage A
R M .
The output current is adjustable from 0.5 A (p-p) to 3 A
(p-p) by varying R M . The maximum input differential
voltage is 1.8 V. In the application it is recommended that
V diff = 1.5 V (typ). This is recommended because of the
spread of input current and the spread in the value of
R CON .
The flyback voltage is determined by an additional supply
voltage V FB . The principle of operating with two supply
voltages (class G) makes it possible to fix the supply
voltage V P optimum for the scan voltage and the second
supply voltage V FB optimum for the flyback voltage. Using
this method, very high efficiency is achieved.
The supply voltage V FB is almost totally available as
flyback voltage across the coil, this being possible due to
the absence of a decoupling capacitor (not necessary, due
to the bridge configuration). The output circuit is fully
protected against the following:
·
R CON = I coil ´
V O(guard)
8
guard output voltage
V I(fb)
9
input feedback voltage
handbook, 2 columns
1
I drive(pos)
I drive(neg)
2
V P
V O(B)
3
4
GND
5
TDA8351
V FB
V O(A)
V O(guard)
6
7
thermal protection
8
·
short-circuit protection of the output pins (pins 4 and 7)
V I(fb)
9
short-circuit of the output pins to V P .
A guard circuit V O(guard) is provided. The guard circuit is
activated at the following conditions:
·
MBC989
during flyback
·
during short-circuit of the coil and during short-circuit of
the output pins (pins 4 and 7) to V P or ground
Metal block connected to substrate pin 5.
Metal on back.
·
during open loop
when the thermal protection is activated.
This signal can be used for blanking the picture tube
screen.
Fig.2 Pin configuration.
December 1994
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·
·
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Philips Semiconductors
Preliminary specification
DC-coupled vertical deflection circuit
TDA8351
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
DC supply
V P
supply voltage
non-operating
-
40
V
-
25
V
V FB
flyback supply voltage
-
50
V
note 1
-
60
V
Vertical circuit
I O(p-p)
output current (peak-to-peak value)
note 2
-
3
A
V O(A)
output voltage (pin 7)
-
52
V
note 1
-
62
V
Flyback switch
I M
peak output current
-
± 1.5
A
Thermal data (in accordance with IEC 747-1)
T stg
storage temperature
- 55
+150
° C
T amb
operating ambient temperature
-
25
+75
°
C
T vj
virtual junction temperature
-
150
° C
R th vj-c
resistance v j -case
-
4
K/W
R th vj-a
resistance v j -ambient in free air
-
40
K/W
t sc
short-circuiting time
note 3
-
1
hr
Notes
1. A flyback supply voltage of
resistor
(dependent on I O and the inductance of the coil) has to be connected between pin 7 and ground. The decoupling
capacitor of V FB has to be connected between pin 6 and pin 3. This supply voltage line must have a resistance of
33
>
50 V up to 60 V is allowed in application. A 220 nF capacitor in series with a 22
W
(see application circuit Fig.6).
2. I O maximum determined by current protection.
3. Up to V P = 18 V.
W
December 1994
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Philips Semiconductors
Preliminary specification
DC-coupled vertical deflection circuit
TDA8351
CHARACTERISTICS
V P = 17.5 V; T amb = 25
°
C; V FB = 45 V; f i = 50 Hz; I I(sb) = 400
m
A; measured in test circuit of Fig.3; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DC supply
V P
operating supply voltage
9.0
-
25
V
V FB
flyback supply voltage
V P
-
50
V
note 1
V P
-
60
V
I P
supply current
no signal; no load
-
30
55
mA
Vertical circuit
V O
output voltage swing (scan)
I diff = 0.6 mA (p-p);
V diff = 1.8 V (p-p);
I O = 3 A (p-p)
19.8
-
-
V
LE
linearity error
I O = 3 A (p-p); note 2
-
1
2
%
I O = 50 mA (p-p); note 2
-
1
2
%
V O
output voltage swing (flyback)
V O(A) - V O(B)
I diff = 0.3 mA;
I O = 1.5 A (M)
-
39
-
V
V DF
forward voltage of the internal
efficiency diode (V O(A) - V FB )
I O = - 1.5 A (M);
I diff = 0.3 mA
-
-
1.5
V
| I os |
output offset current
I diff = 0;
I I(sb) = 50 to 500 m A
-
-
30
mA
| V os |
offset voltage at the input of the
feedback amplifier (V I(fb) - V O(B) )
I diff = 0;
I I(sb) = 50 to 500 m A
-
-
18
mV
D V os T
output offset voltage as a function
of temperature
I diff = 0
-
-
72
m V/K
V O(A)
DC output voltage
I diff = 0; note 3
-
8.0
-
V
G vo
open-loop voltage gain (V 7-4 /V 1-2 ) notes 4 and 5
-
80
-
dB
open loop voltage gain
(V 7-4 /V 9-4 ; V 1-2 = 0)
note 4
-
80
-
dB
V R
voltage ratio V 1-2 /V 9-4
-
0
-
dB
f res
frequency response ( - 3 dB)
open loop; note 6
-
40
-
Hz
G I
current gain (I O /I diff )
-
5000
-
D G c T
current gain drift as a function of
temperature
-
-
10 - 4
K
I I(sb)
signal bias current
50
400
500
m A
I FB
flyback supply current
during scan
-
-
100
m A
PSRR
power supply ripple rejection
note 7
-
80
-
dB
V I(DC)
DC input voltage
-
2.7
-
V
V I(CM)
common mode input voltage
I I(sb) = 0
0
-
1.6
V
I bias
input bias current
I I(sb) = 0
-
0.1
0.5
m A
I O(CM)
common mode output current
D I I(sb) = 300 m A (p-p);
f i = 50 Hz; I diff = 0
-
0.2
-
mA
December 1994
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