attiny24_44_84.pdf

Features

• High Performance, Low Power AVR ® 8-Bit Microcontroller

Advanced RISC Architecture

– 120 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

Non-Volatile Program and Data Memories

– 2/4/8K Bytes of In-System Programmable Program Memory Flash

Endurance: 10,000 Write/Erase Cycles

– 128/256/512 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– 128/256/512 Bytes of Internal SRAM

– Data retention: 20 years at 85 ° C / 100 years at 25 ° C

– Programming Lock for Self-Programming Flash & EEPROM Data Security

Peripheral Features

– One 8-Bit and One 16-Bit Timer/Counter with Two PWM Channels, Each

– 10-bit ADC

8 Single-Ended Channels

12 Differential ADC Channel Pairs with Programmable Gain (1x / 20x)

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-Chip Analog Comparator

– Universal Serial Interface

Special Microcontroller Features

– debugWIRE On-chip Debug System

– In-System Programmable via SPI Port

– Internal and External Interrupt Sources: Pin Change Interrupt on 12 Pins

– Low Power Idle, ADC Noise Reduction, Standby and Power-Down Modes

– Enhanced Power-on Reset Circuit

– Programmable Brown-Out Detection Circuit

– Internal Calibrated Oscillator

– On-Chip Temperature Sensor

I/O and Packages

– Available in 20-Pin QFN/MLF & 14-Pin SOIC and PDIP

– Twelve Programmable I/O Lines

Operating Voltage:

– 1.8 – 5.5V for ATtiny24V/44V/84V

– 2.7 – 5.5V for ATtiny24/44/84

Speed Grade

– ATtiny24V/44V/84V

0 – 4 MHz @ 1.8 – 5.5V

0 – 10 MHz @ 2.7 – 5.5V

– ATtiny24/44/84

0 – 10 MHz @ 2.7 – 5.5V

0 – 20 MHz @ 4.5 – 5.5V

Industrial Temperature Range: -40 ° C to +85 ° C

Low Power Consumption

– Active Mode (1 MHz System Clock): 300 µA @ 1.8V

– Power-down Mode: 0.1 µA @ 1.8V

8-bit

Microcontroller

with 2/4/8K

Bytes In-System

Programmable

Flash

ATtiny24/44/84

Preliminary

Rev. 8006G–AVR–01/08

1. Pin Configurations

Figure 1-1. Pinout ATtiny24/44/84

PDIP/SOIC

VCC

(PCINT8/XTAL1/CLKI) PB0

(PCI NT9/XT AL2) PB1

(PCINT11/RESET/dW) PB3

(PCINT10/INT0/OC0A/CKOUT) PB2

(PCINT7/ICP/OC0B/ADC7) PA7

(PCINT6/OC1A/SDA/MOSI/DI/ADC6) PA6

GND

PA0 (ADC0/AREF/PCINT0)

PA1 (ADC1/AIN0/PCINT1)

PA2 (ADC2/AIN1/PCINT2)

PA3 (ADC3/T0/PCINT3)

PA4 (ADC4/USCK/SCL/T1/PCINT4)

PA5 (ADC5/DO/MISO/OC1B/PCINT5)

QFN/MLF

Pin 16: PA6 (PCINT6/OC1A/SDA/MOSI/DI/ADC6)

Pin 20: PA5 (ADC5/DO/MISO/OC1B/PCINT5)

(ADC4/USCK/SCL/T1/PCINT4) PA4

(ADC3/T0/PCINT3) PA3

(ADC2/AIN1/PCINT2) PA2

(ADC1/AIN0/PCINT1) PA1

(ADC0/AREF/PCINT0) PA0

PA7 (PCINT7/ICP/OC0B/ADC7)

PB2 (PCINT10/ INT0/OC 0A/CKOUT)

PB3 (PCINT11/RESET/dW)

PB1 (PCINT9/XTAL2)

PB0 (PCINT8/XTAL1/CLKI)

NOTE

Bottom pad should be

soldered to ground.

DNC: Do Not Connect

1.1 Pin Descriptions

1.1.1

VCC

Supply voltage.

1.1.2

GND

Ground.

1.1.3

Port B (PB3...PB0)

Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmet rical dri ve characteristics with both high sink and source

capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of

RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low

will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

ATtiny24/44/84

8006G–AVR–01/08

ATtiny24/44/84

Port B also serves the functions of various special features of the ATtiny24/44/84 as listed in

Section 10.3 “Alternate Port Functions” on page 57 .

1.1.4

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running and provided the reset pin has not been disabled. The min-

imum pulse length is given in Table 20-4 on page 179 . Shorter pulses are not guaranteed to

generate a reset.

The reset pin can also be used as a (weak) I/O pin.

1.1.5

Port A (PA7...PA0)

Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port A has alternate functions as analog inputs for the ADC, analog comparator, timer/counter,

SPI and pin change interrupt as described in “Alternate Port Functions” on page 57 .

8006G–AVR–01/08

2. Overview

The ATtiny24/44/84 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced

RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny24/44/84

achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize

power consumption versus processing speed.

Figure 2-1. Block Diagram

VCC

8-BIT DATABUS

INTERNAL

OSCILLATOR

CALIBRATED

OSCILLATOR

GND

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

TIMING AND

CONTROL

PROGRAM

FLASH

SRAM

MCU CONTROL

INSTRUCTION

GENERAL

PURPOSE

REGISTERS

MCU STATUS

TIMER/

COUNTER0

INSTRUCTION

DECODER

TIMER/

COUNTER1

CONTROL

LINES

ALU

STATUS

INTERRUPT

UNIT

PROGRAMMING

LOGIC

ISP INTERFACE

EEPROM

OSCILLATORS

DATA REGISTER

PORT A

DATA DIR.

REG.PORT A

ADC

DATA REGISTER

PORT B

DATA DIR.

REG.PORT B

PORT A DRIVERS

PORT B DRIVERS

PA7-PA0

PB3-PB0

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32

registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

ATtiny24/44/84

8006G–AVR–01/08

ATtiny24/44/84

The ATtiny24/44/84 provides the following features: 2/4/8K byte of In-System Programmable

Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O lines, 32

general purpose working registers, a 8-bit Timer/Counter with two PWM channels, a 16-bit

timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC,

programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable

Watchdog Timer with internal Oscillator, internal calibrated oscillator, and four software select-

able power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter,

ADC, Analog Comparator, and Interrupt system to continue functioning. ADC Noise Reduction

mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O mod-

ules except the ADC. In Power-down mode registers keep their contents and all chip functions

are disbaled until the next interrupt or hardware reset. In Standby mode, the crystal/resonator

oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined

with low power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The on-

chip ISP Flash allows the Program memory to be re-programmed in-system through an SPI

serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code

running on the AVR core.

The ATtiny24/44/84 AVR is supported with a full suite of program and system development tools

including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits.

8006G–AVR–01/08

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