attiny15.pdf

Features

• High-performance, Low-power AVR ® 8-bit Microcontroller

Advanced RISC Architecture

– 90 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

Non-volatile Program and Data Memories

– 1K Byte In-System Programmable Flash Program Memory

Endurance: 1,000 Write/Erase Cycles

– 64 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– Programming Lock for Flash Program Data Security

Peripheral Features

– Interrupt and Wake-up on Pin Change

– Two 8-bit Timer/Counters with Separate Prescalers

– One 150 kHz, 8-bit High-speed PWM Output

– 4-channel 10-bit ADC

One Differential Voltage Input with Optional Gain of 20x

– On-chip Analog Comparator

– Programmable Watchdog Timer with On-chip Oscillator

Special Microcontroller Features

– In-System Programmable via SPI Port

– Enhanced Power-on Reset Circuit

– Programmable Brown-out Detection Circuit

– Internal, Calibrated 1.6 MHz Tunable Oscillator

– Internal 25.6 MHz Clock Generator for Timer/Counter

– External and Internal Interrupt Sources

– Low-power Idle and Power-down Modes

Power Consumption at 1.6 MHz, 3V, 25 ° C

– Active: 3.0 mA

– Idle Mode: 1.0 mA

– Power-down: < 1 µA

I/O and Packages

– 8-lead PDIP and 8-lead SOIC: 6 Programmable I/O Lines

Operating Voltages

– 2.7V - 5.5V

Internal 1.6 MHz System Clock

8-bit

Microcontroller

with 1K Byte

Flash

ATtiny15L

Pin Configuration

PDIP/SOIC

(RESET/ADC0) PB5

(ADC3) PB4

(ADC2) PB3

GND

VCC

PB2 (ADC1/SCK/T0/INT0)

PB1 (AIN1/MISO/OC1A)

PB0 (AIN0/AREF/MOSI)

Not recommended for new

design

Rev. 1187H–AVR–09/07

Description

The ATtiny15L is a low-power CMOS 8-bit microcontroller based on the AVR RISC

architecture. By executing powerful instructions in a single clock cycle, the ATtiny15L

achieves throughputs approaching 1 MIPS per MHz allowing the system designer to

optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting architecture is more code efficient while achieving throughputs up to

ten times faster than conventional CISC microcontrollers.

The ATtiny15L provides 1K byte of Flash, 64 bytes EEPROM, six general purpose I/O

lines, 32 general purpose working registers, two 8-bit Timer/Counters, one with high-

speed PWM output, internal Oscillators, internal and external interrupts, programmable

Watchdog Timer, 4-channel 10-bit Analog-to-Digital Converter with one differential volt-

age input with optional 20x gain, and three software-selectable Power-saving modes.

The Idle mode stops the CPU while allowing the ADC, anAlog Comparator,

Timer/Counters and interrupt system to continue functioning. The ADC Noise Reduction

mode facilitates high-accuracy ADC measurements by stopping the CPU while allowing

the ADC to continue functioning. The Power-down mode saves the register contents but

freezes the Oscillators, disabling all other chip functions until the next interrupt or Hard-

ware Reset. The wake-up or interrupt on pin change features enable the ATtiny15L to

be highly responsive to external events, still featuring the lowest power consumption

while in the Power-saving modes.

The device is manufactured using Atmel’s high-density, Non-volatile memory technol-

ogy. By combining a RISC 8-bit CPU with Flash on a monolithic chip, the ATtiny15L is a

powerful microcontroller that provides a highly flexible and cost-efficient solution to

many embedded control applications. The peripheral features make the ATtiny15L par-

ticularly suited for battery chargers, lighting ballasts and all kinds of intelligent sensor

applications.

The ATtiny15L AVR is supported with a full suite of program and system development

tools including macro assemblers, program debugger/simulators, In-circuit emulators

and evaluation kits.

ATtiny15L

1187H–AVR–09/07

ATtiny15L

Block Diagram

Figure 1. The ATtiny15L Block Diagram

VCC

8-BIT DATA BUS

TUNABLE

INTERNAL

OSCILLATOR

INTERNAL

OSCILLATOR

GND

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

TIMING AND

CONTROL

PROGRAM

FLASH

HARDWARE

STACK

MCU CONTROL

INSTRUCTION

GENERAL

PURPOSE

REGISTERS

MCU STATUS

INSTRUCTION

DECODER

TIMER/

COUNTER0

CONTROL

LINES

ALU

TIMER/

COUNTER1

STATUS

INTERRUPT

UNIT

PROGRAMMING

LOGIC

ISP MODULE

DATA

EEPROM

ANALOG MUX

ADC

DATA REGISTER

PORT B

DATA DIR.

REG.PORT B

PORT B DRIVERS

PB0-PB5

1187H–AVR–09/07

Pin Descriptions

VCC

Supply voltage pin.

GND

Ground pin.

Port B (PB5..PB0)

Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected

for each bit). PB5 is input or open-drain output. The use of pin PB5 is defined by a fuse

and the special function associated with this pin is External Reset. The port pins are tri-

stated when a reset condition becomes active, even if the clock is not running.

Port B also accommodates analog I/O pins. The Port B pins with alternate functions are

shown in Table 1.

Table 1. Port B Alternate Functions

Port Pin

Alternate Function

PB0

MOSI (Data Input Line for Memory Downloading)

AREF (ADC Voltage Reference)

AIN0 (Analog Comparator Positive Input)

PB1

MISO (Data Output Line for Memory Downloading)

OC1A (Timer/Counter PWM Output)

AIN1 (Analog Comparator Negative Input)

PB2

SCK (Serial Clock Input for Serial Programming)

INT0 (External Interrupt0 Input)

ADC1 (ADC Input Channel 1)

T0 (Timer/Counter0 External Counter Input)

PB3

ADC2 (ADC Input Channel 2)

PB4

ADC3 (ADC Input Channel 3)

PB5

RESET (External Reset Pin)

ADC0 (ADC Input Channel 0)

Analog Pins

Up to four analog inputs can be selected as inputs to Analog-to-Digital Converter (ADC).

Internal Oscillators

The internal Oscillator provides a clock rate of nominally 1.6 MHz for the system clock

(CK). Due to large initial variation (0.8 -1.6 MHz) of the internal Oscillator, a tuning capa-

bility is built in. Through an 8-bit control register – OSCCAL – the system clock rate can

be tuned with less than 1% steps of the nominal clock.

There is an internal PLL that provides a 16x clock rate locked to the system clock (CK)

for the use of the Peripheral Timer/Counter1. The nominal frequency of this peripheral

clock, PCK, is 25.6 MHz.

ATtiny15L

1187H–AVR–09/07

ATtiny15L

AT tiny 15 L

Architectural

Overview

The fast-access Register File concept contains 32 x 8-bit general purpose working reg-

isters with a single-clock-cycle access time. This means that during one single clock

cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output

from the Register File, the operation is executed, and the result is stored back in the

Two of the 32 registers can be used as a 16-bit pointer for indirect memory access. This

pointer is called the Z-pointer, and can address the Register File, IO file and the Flash

Program memory.

Figure 2. The ATtiny15L AVR RISC Architecture

Data Bus 8-bit

Control

Registrers

Program

Counter

Status

and Test

512 x 16

Program

FLASH

Interrupt

Unit

Instruction

32 x 8

General

Purpose

Registrers

SPI Unit

2 x 8-bit

Timer/Counter

Direct Addressing

Instruction

Decoder

Watchdog

Timer

ALU

Control Lines

ADC

64 x 8

EEPROM

Analog

Comparator

I/O Lines

The ALU supports arithmetic and logic functions between registers or between a con-

stant and a register. Single-register operations are also executed in the ALU. Figure 2

shows the ATtiny15L AVR RISC microcontroller architecture. The AVR uses a Harvard

architecture concept with separate memories and buses for program and data memo-

ries. The program memory is accessed with a two-stage pipeline. While one instruction

is being executed, the next instruction is pre-fetched from the program memory. This

concept enables instructions to be executed in every clock cycle. The Program memory

is In-System Programmable Flash memory.

With the relative jump and relative call instructions, the whole address space is directly

accessed. All AVR instructions have a single 16-bit word format, meaning that every

program memory address contains a single 16-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is

stored on the Stack. The Stack is a 3-level-deep Hardware Stack dedicated for subrou-

tines and interrupts.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control

Registers, Timer/Counters and other I/O functions. The memory spaces in the AVR

architecture are all linear and regular memory maps.

1187H–AVR–09/07

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