atmega16.pdf

Features

• High-performance, Low-power AVR ® 8-bit Microcontroller

Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

High Endurance Non-volatile Memory segments

– 16K Bytes of In-System Self-programmable Flash program memory

– 512 Bytes EEPROM

– 1K Byte Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C (1)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security

JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Four PWM Channels

– 8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels in TQFP Package Only

2 Differential Channels with Programmable Gain at 1x, 10x, or 200x

– Byte-oriented Two-wire Serial Interface

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby

and Extended Standby

I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF

Operating Voltages

– 2.7 - 5.5V for ATmega16L

– 4.5 - 5.5V for ATmega16

Speed Grades

– 0 - 8 MHz for ATmega16L

– 0 - 16 MHz for ATmega16

Power Consumption @ 1 MHz, 3V, and 25 ⋅ C for ATmega16L

– Active: 1.1 mA

– Idle Mode: 0.35 mA

– Power-down Mode: < 1 µA

8-bit

Microcontroller

with 16K Bytes

In-System

Programmable

Flash

ATmega16

ATmega16L

Note: Not recommended for new

designs.

Rev. 2466S–AVR–05/09

ATmega16(L)

Configurations

Figure 1. Pinout ATmega16

PDIP

(XCK/T0) PB0

(T1) PB1

(INT2/AIN0) PB2

(OC0/AIN1) PB3

(SS) PB4

(MOSI) PB5

(MISO) PB6

(SCK) PB7

RESET

VCC

GND

XTAL2

XTAL1

(RXD) PD0

(TXD) PD1

(INT0) PD2

(INT1) PD3

(OC1B) PD4

(OC1A) PD5

(ICP1) PD6

PA0 (ADC0)

PA1 (ADC1)

PA2 (ADC2)

PA3 (ADC3)

PA4 (ADC4)

PA5 (ADC5)

PA6 (ADC6)

PA7 (ADC7)

AREF

GND

AVCC

PC7 (TOSC2)

PC6 (TOSC1)

PC5 (TDI)

PC4 (TDO)

PC3 (TMS)

PC2 (TCK)

PC1 (SDA)

PC0 (SCL)

PD7 (OC2)

TQFP/QFN/MLF

(MOSI) PB5

(MISO) PB6

(SCK) PB7

RESET

VCC

GND

XTAL2

XTAL1

(RXD) PD0

(TXD) PD1

(INT0) PD2

PA4 (ADC4)

PA5 (ADC5)

PA6 (ADC6)

PA7 (ADC7)

AREF

GND

AVCC

PC7 (TOSC2)

PC6 (TOSC1)

PC5 (TDI)

PC4 (TDO)

NOTE:

Bottom pad should

be soldered to ground.

Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of

other AVR microcontrollers manufactured on the same process technology. Min and Max values

will be available after the device is characterized.

2466S–AVR–05/09

ATmega16(L)

Overview

The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC

architecture. By executing powerful instructions in a single clock cycle, the ATmega16 achieves

throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-

sumption versus processing speed.

Block Diagram

Figure 2. Block Diagram

PA0 - PA7

PC0 - PC7

VCC

PORTA DRIVERS/BUFFERS

PORTC DRIVERS/BUFFERS

GND

PORTA DIGITAL INTERFACE

PORTC DIGITAL INTERFACE

AVCC

MUX &

ADC

INTERFACE

TWI

AREF

PROGRAM

COUNTER

STACK

POINTER

TIMERS/

COUNTERS

OSCILLATOR

PROGRAM

FLASH

SRAM

INTERNAL

OSCILLATOR

XTAL 1

INSTRUCTION

GENERAL

PURPOSE

REGISTERS

WATCHDOG

TIMER

OSCILLATOR

XTAL2

INSTRUCTION

DECODER

MCU CTRL.

& TIMING

RESET

CONTROL

LINES

ALU

INTERRUPT

UNIT

INTERNAL

CALIBRATED

OSCILLATOR

AVR CPU

STATUS

EEPROM

PROGRAMMING

LOGIC

SPI

USART

COMP.

INTERFACE

PORTB DIGITAL INTERFACE

PORTD DIGITAL INTERFACE

PORTB DRIVERS/BUFFERS

PORTD DRIVERS/BUFFERS

PB0 - PB7

PD0 - PD7

2466S–AVR–05/09

ATmega16(L)

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATmega16 provides the following features: 16K bytes of In-System Programmable Flash

Program memory with Read-While-Write capabilities, 512 bytes EEPROM, 1K byte SRAM, 32

general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-

scan, On-chip Debugging support and programming, three flexible Timer/Counters with com-

pare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented

Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with

programmable gain (TQFP package only), a programmable Watchdog Timer with Internal Oscil-

lator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops

the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters,

SPI port, and interrupt system to continue functioning. The Power-down mode saves the register

contents but freezes the Oscillator, disabling all other chip functions until the next External Inter-

rupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run,

allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC

Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and

ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/reso-

nator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up

combined with low-power consumption. In Extended Standby mode, both the main Oscillator

and the Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high density nonvolatile memory technology. The On-

chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial

interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program

running on the AVR core. The boot program can use any interface to download the application

program in the Application Flash memory. Software in the Boot Flash section will continue to run

while the Application Flash section is updated, providing true Read-While-Write operation. By

combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,

the Atmel ATmega16 is a powerful microcontroller that provides a highly-flexible and cost-effec-

tive solution to many embedded control applications.

The ATmega16 AVR is supported with a full suite of program and system development tools

including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators,

and evaluation kits.

Pin Descriptions

VCC

Digital supply voltage.

GND

Ground.

Port A (PA7..PA0)

Port A serves as the analog inputs to the A/D Converter.

Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit). The Port A output buffers have sym-

metrical drive characteristics with both high sink and source capability. When pins PA0 to PA7

are used as inputs and are externally pulled low, they will source current if the internal pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

2466S–AVR–05/09

ATmega16(L)

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the ATmega16 as listed on page

58 .

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins

PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs.

Port C also serves the functions of the JTAG interface and other special features of the

ATmega16 as listed on page 61 .

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the ATmega16 as listed on page

63 .

RESET

Reset Input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page

38 . Shorter pulses are not guaranteed to generate a reset.

XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting Oscillator amplifier.

AVCC

AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally con-

nected to V CC , even if the ADC is not used. If the ADC is used, it should be connected to V CC

through a low-pass filter.

AREF

AREF is the analog reference pin for the A/D Converter.

2466S–AVR–05/09

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika: