74HC_HCT7731_CNV_3.pdf

(42 KB) Pobierz
Quad 64-bit static shift register
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
·
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7731
Quad 64-bit static shift register
Product specification
File under Integrated Circuits, IC06
September 1993
21702100.051.png
Philips Semiconductors
Product specification
Quad 64-bit static shift register
74HC/HCT7731
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T amb = 25 ° C; t r = t f = 6 ns.
·
Frequency range DC to 100 MHz.
·
Separate serial data inputs
TYP.
SYMBOL
PARAMETER
CONDITIONS
UNIT
·
Cascadable
HC HCT
·
Functionally compatible with
HEF 4731
t PHL /t PLH
propagation delay
CP a-d to Q a-d
C L = 15 pF;
V CC = 5 V
15 20
ns
·
Includes recycling mode
f max
maximum clock
frequency
100 100
MHz
·
Direct shift out
·
Output capability: Standard
C I
input capacitance
3.5 3.5
pF
·
I CC category: LSI.
C PD
power dissipation
capacitance per register
notes 1, 2
and 3
58 61
pF
APPLICATIONS
Notes
1. C PD is used to determine the dynamic power dissipation (P D in
·
Data storage
m
W):
·
Delay line.
P D = (C PD x V CC 2 x f i ) + (C L + V CC 2 x f o ) + (I pull-up x V CC )
where:
f i = input frequency in MHz.
f o = output frequency in MHz.
V CC = supply voltage in V.
C L = output load capacitance in pF.
I pull-up = pull-up currents in
GENERAL DESCRIPTION
The HC/HCT7731 are high-speed
Si-gate CMOS devices. They are
specified in compliance with JEDEC
standard no. 7A.
m
A.
The HC/HCT7731 are quad 64-bit
static shift registers with a recycling
mode. Each register has separate
data inputs D a to D d , clock inputs CP a
to CP d and data outputs Q a to Q d .
Data shifts one place towards the
output, each LOW to HIGH transition
of the clock pulse. Each recycling
mode input controls two registers
REC ab for registers A and B and
REC cd for registers C and D. When
the REC input is HIGH, the device is
in the recycling mode and data at the
output is shifted back into the input of
the register, so after 64 clock pulses
the contents of a register is again in
its original position. This enables the
user to tap off data from any position.
When the REC input is LOW external
data can be shifted in.
2. For HC the condition is V I = GND to V CC
For HCT the condition is V I = GND to V CC -
1.5 V.
3. See also power dissipation information.
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
PACKAGE
PINS PIN POSITION MATERIAL
CODE
74HC/HCT7731N
16
DIL
plastic
SOT38Z
74HC/HCT7731D
16
SO16
plastic
SOT109A
September 1993
2
21702100.059.png 21702100.060.png
Philips Semiconductors
Product specification
Quad 64-bit static shift register
74HC/HCT7731
PINNING
SYMBOL
PIN
DESCRIPTION
Q a to Q d
1, 7, 9, 15 data outputs
handbook, halfpage
CP a to CP d
2, 6, 10, 14 clock inputs
Q a
1
16
V CC
Q d
CP d
D a to D d
3, 5, 11, 13 data inputs
CP a
2
15
REC ab , REC cd
4, 12
recycled enable input
D a
3
14
GND
8
ground (0 V)
D d
REC ab
D b
4
13
V CC
16
positive supply
7731
5
12
REC cd
D c
CP c
Q c
CP b
6
11
Q b
7
10
GND
8
9
MBA341
Fig.1 Pin configuration.
handbook, full pagewidth
3
D a
MUX
64 - BIT
STATIC SHIFT
REGISTER
Q a
1
CP a
2
4
REC ab
D b
CP b
5
MUX
64 - BIT
STATIC SHIFT
REGISTER
Q b
7
6
11
D c
MUX
64 - BIT
STATIC SHIFT
REGISTER
Q c
9
10
CP c
12
REC cd
13
D d
MUX
64 - BIT
STATIC SHIFT
REGISTER
Q d
15
14
CP d
MBA342
Fig.2 Functional diagram.
September 1993
3
21702100.061.png 21702100.001.png 21702100.002.png 21702100.003.png 21702100.004.png 21702100.005.png 21702100.006.png 21702100.007.png 21702100.008.png 21702100.009.png 21702100.010.png 21702100.011.png 21702100.012.png 21702100.013.png 21702100.014.png 21702100.015.png 21702100.016.png 21702100.017.png 21702100.018.png 21702100.019.png 21702100.020.png 21702100.021.png 21702100.022.png 21702100.023.png 21702100.024.png 21702100.025.png 21702100.026.png 21702100.027.png 21702100.028.png 21702100.029.png 21702100.030.png 21702100.031.png 21702100.032.png 21702100.033.png 21702100.034.png
Philips Semiconductors
Product specification
Quad 64-bit static shift register
74HC/HCT7731
handbook, full pagewidth
REC n
DQ
DQ
DQ
Q n
D n
FF1
FF2
FF64
CP
CP
CP
CP n
MBA345
to second shift register
Fig.3 Logic diagram.
FUNCTION TABLE
INPUT
OUTPUT
REC
CP
MODE
L
­
shift
H
­
recycle
Notes
1. L = LOW voltage level
H = HIGH voltage Level
­
September 1993
4
= LOW-to-HIGH CP transition
21702100.035.png 21702100.036.png 21702100.037.png 21702100.038.png 21702100.039.png 21702100.040.png 21702100.041.png 21702100.042.png 21702100.043.png 21702100.044.png 21702100.045.png 21702100.046.png 21702100.047.png 21702100.048.png 21702100.049.png 21702100.050.png 21702100.052.png 21702100.053.png 21702100.054.png 21702100.055.png 21702100.056.png 21702100.057.png
Philips Semiconductors
Product specification
Quad 64-bit static shift register
74HC/HCT7731
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications” .
Output capability: standard
I CC category: LSI.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t r = t f = 6 ns; C L = 50 pF.
T amb (
°
C)
TEST CONDITION
SYMBOL PARAMETER
+
25
-
40 to
+
85
-
40 to
+
125
UNIT
V CC
(V)
WAVEFORMS
MIN TYP MAX MIN MAX MIN MAX
t PHL /t PLH propagation
delay time CP
to Q n
-
-
-
50
18
15
155
31
26
-
-
-
190
38
32
-
-
-
230
46
39
ns
ns
ns
2.0
4.5
6.0
Fig.4
t THL /t TLH output transition
time
-
-
-
19
7
6
75
15
13
-
-
-
90
18
15
-
-
-
110
22
19
ns
ns
ns
2.0
4.5
6.0
Fig.4
t W
clock pulse
width
HIGH or LOW
80
16
14
19
7
6
-
-
-
100
20
17
-
-
-
120
24
20
-
-
-
ns
ns
ns
2.0
4.5
6.0
Fig.4
t su
set-up time D n
to CP n
60
12
10
8
3
3
-
-
-
75
15
13
-
-
-
90
18
15
-
-
-
ns
ns
ns
2.0
4.5
6.0
Fig.4
t su
set-up time
REC n to CP n
75
15
13
22
8
7
-
-
-
90
18
15
-
-
-
110
22
19
-
-
-
ns
ns
ns
2.0
4.5
6.0
Fig.5
t h
hold time D n to
CP n
25
5
4
- 3
-
-
-
-
30
6
5
-
-
-
35
7
6
-
-
-
ns
ns
ns
2.0
4.5
6.0
Fig.4
1
-
1
t h
hold time REC n
to CP n
10
2
2
-
8
-
-
-
10
2
2
-
-
-
15
3
3
-
-
-
ns
ns
ns
2.0
4.5
6.0
Fig.5
3
- 3
f max
maximum clock
pulse frequency
6
30
35
26
78
93
-
-
-
4.8
24
28
-
-
-
4
20
23
-
-
-
MHz
MHZ
MHz
2.0
4.5
6.0
Fig.4 (note 1)
Note
1. The maximum power dissipation has to be observed. See power dissipation information.
September 1993
5
-
21702100.058.png

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin