74HC_HCT7080_CNV_2.pdf

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16-bit even/odd parity generator/checker
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
·
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7080
16-bit even/odd parity
generator/checker
Product specification
File under Integrated Circuits, IC06
December 1990
21702037.005.png
Philips Semiconductors
Product specification
16-bit even/odd parity
generator/checker
74HC/HCT7080
FEATURES
The 74HC/HCT7080 are 16-bit parity generators or
checkers commonly used to detect errors in high-speed
data transmission or data retrieval systems.
·
Word-length easily expanded by cascading
·
Generates either even or odd parity for 16-data bits
The even and odd parity output is available for generating
or checking even/odd parity up to 16-bits.
·
Output capability: standard
·
I CC category: MSI
The even/odd parity output (E/O) is HIGH when an even
number of data inputs (I 0 to I 15 ) are H IGH and the
cascade/even-odd-changing input (X) is HIGH.
Expansion to larger word sizes is accomp lis hed by
connecting the even/odd parity out pu t (E/O) to the
cascade/even-odd-changing input (X) of the final stage.
GENERAL DESCRIPTION
The 74HC/HCT7080 are high-speed Si-gate CMOS
devices. They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T amb =25
°
C; t r =t f = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
t PHL/ t PLH
propagati on delay
C L = 15 pF; V CC =5 V
I n to E/ O
92s
X to E/O
25s
I
input capacitance
3.5
3.5
pF
C PD
power dissipation capacitance per package
notes 1 and 2
24
25
pF
Notes
1. C PD is used to determine the dynamic power dissipation (P D in
m
W):
P D =C PD ´
V CC 2
´
f i + å
(C L ´
V CC 2
´
f o ) where:
f o ) = sum of outputs
C L = output load capacitance in pF
V CC = supply voltage in V
2. For HC the condition is V I = GND to V CC
For HCT the condition is V I = GND to V CC -
f i = input frequency in MHz
f o = output frequency in MHz
å
(C L ´
V CC 2
´
1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information” .
December 1990
2
21702037.006.png 21702037.007.png
Philips Semiconductors
Product specification
16-bit even/odd parity generator/checker
74HC/HCT7080
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
X
cascade/even-odd-changing input
2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18
I 0 to I 15
data inputs
10
G ND
ground (0 V)
19
E/O
even/odd parity output
20
V CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
21702037.008.png 21702037.001.png
Philips Semiconductors
Product specification
16-bit even/odd parity generator/checker
74HC/HCT7080
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS
OUTPUTS
I n
X
E/O
å =E
H
L
H
L
å¹
E
H
L
L
H
Fig.5 Logic diagram.
Notes
1. H = HIGH voltage level
L = LOW voltage level
E = even
December 1990
4
21702037.002.png 21702037.003.png
Philips Semiconductors
Product specification
16-bit even/odd parity generator/checker
74HC/HCT7080
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications” .
Output capability: standard
I CC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t r =t f = 6 ns; C L = 50 pF
T amb (
°
C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
+
25
-
40 to
+
85
-
40 to
+
125
V CC
(V)
WAVEFORMS
min. typ. max. min. max. min. max.
t PHL / t PLH propaga tio n delay
I n to E/O
91
33
26
280
56
48
350
70
60
420
84
71
ns
2.0
4.5
6.0
Fig.7
t PHL / t PLH p ro paga tio n delay
X to E/O
41
15
12
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.6
t THL / t TLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Figs 6 and 7
December 1990
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