2732-200.pdf

M2732A

NMOS 32 Kbit (4Kb x 8) UV EPROM

NOT FOR NEW DESIGN

FAST ACCESS TIME: 200ns

EXTENDED TEMPERATURE RANGE

SINGLE 5V SUPPLY VOLTAGE

LOW STANDBY CURRENT: 35mA max

INPUTS and OUTPUTS TTL COMPATIBLE

DURING READ and PROGRAM

COMPLETELY STATIC

DESCRIPTION

The M2732A is a 32,768 bit UV erasable and elec-

trically programmable memory EPROM. It is orga-

nized as 4,096 words by 8 bits. The M2732A with

its single 5V power supply and with an access time

of 200 ns, is ideal suited for applications where

fast turn around and pattern experimentation are

important requirements.

The M2732A is housed in a 24 pin Window Ce-

ramic Frit-Seal Dual-in-Line package. The trans-

parent lid allows the user to expose the chip to

ultraviolet light to erase the bit pattern. A new pat-

tern can be then written to the device by following

the programming procedure.

FDIP24W (F)

Figure 1. Logic Diagram

V CC

A0-A11

Q0-Q7

M2732A

GV PP

V SS

AI00780B

November 2000

This is information on a product still in production but not recommended for new designs.

1/9

M2732A

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

T A

Ambient Operating Temperature

grade 1

grade 6

0 to 70

–40 to 85

T BIAS

Temperature Under Bias

grade 1

grade 6

–10 to 80

–50 to 95

V IO Input or Output Voltages –0.6 to 6 V

V CC Supply Voltage –0.6 to 6 V

V PP Program Supply Voltage –0.6 to 22 V

Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause

permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those

indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for ex tended periods

may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

T STG

Storage Temperature

–65 to 125

Figure 2. DIP Pin Connections

be used to gate data to the output pins, inde-

pendent of device selection.

Assuming that the addresses are stable, add re ss

access time (t AVAQ ) is equal to the delay from E to

output (t ELQV ). Da ta is available at t he outputs after

the falling edge of G, assuming that E has been low

and the addresses have been stable for at least

t AVQV -t GLQV .

Standby Mode

The M2732A has a standby mode which reduces

the active power current by 70 %, from 125 mA to

35 mA. The M2732A is placed in t he standby mode

by applying a TTL high signal to E input. When in

standby mode, the outputs a re in a high impedance

state, independent of the GV PP input.

Two Line Output Control

Because M2732A’s are usually used in larger mem-

ory arrays, this product features a 2 line control

function which accommodates the use of multiple

memory connection. The two line control function

allows:

a. the lowest possible memory power dissipation,

b. complete assurance that output bus contention

will not occur.

To most efficiently us e these two control lines, it is

recommended that E be decoded and us ed as the

primary device selecting function, while G should

be made a common connectio n to all devices in the

array and connected to the READ line from the

system control bus.

This ensures that all deselected memory devices

are in their low power standby mode and that the

output pins are only active when data is required

from a particular memory device.

V CC

A11

GV PP

M2732A

A10

V SS

AI00781

DEVICE OPERATION

The six modes of operation for the M2732A are

listed in the Operating Modes Table. A single 5V

power supply is required in the read mode. All

inputs are TTL level except for V PP.

Read Mode

The M2732A has two control functions, both of

which must be logically satisfied i n o rder to obtain

data at the outputs. Chip Enable (E) is the power

control and sh ou ld be used for device selection.

Output Enable (G) is the output control and should

2/9

M2732A

F capacitor must be

placed across GV PP and ground to suppress spu-

rious voltage transients which may damage the

device. The data to be programmed is applied, 8

bits in parallel, to the data output pins. The levels

required for the address and data inputs are TTL.

When the address and data are stable, a 50m s,

active low, TTL program pulse is applied to the E

input. A program pulse must be applied at each

address location to be programmed. Any location

can be programmed at any time - either individually,

sequentially, or at random. The program pulse has

a maximum width of 55ms. The M2732A must n ot

be programmed with a DC signal applied to the E

input.

Programming of multiple M2732As in parallel with

the same data can be easily accomplished due to

the simplicity of the programming requirements.

Inputs of the paralleled M2732As may be con-

nected together when they are programmed with

th e same data. A low level TTL pulse applied to the

E input programs the paralleled 2732As.

Program Inhibit

Programming of multiple M2732As in parallel with

diff er ent data is also easily a cc omplished. Except

for E, all like inputs (including GV PP ) of the parallel

M2732As may be common. A TTL level program

pulse applied to a M2732A’s E input with GV PP at

21V will program that M2732A. A high level E input

inhibits the other M2732As from being pro-

grammed.

Program Verify

A verify should be performed on the programmed

bits to determine that they were corr ec tly pro-

g rammed. The verify is carried out with GV PP and

E at V IL .

ERASURE OPERATION

The erasure characteristics of the M2732A are

such that erasure begins when the cells are ex-

posed to light with wavelengths shorter than ap-

proximately 4000 Å. It should be noted that sunlight

and certain types of fluorescent lamps have wave-

lengths in the 3000-4000 Å range. Research shows

that constant exposure to room level fluorescent

lighting could erase a typical M2732A in approxi-

mately 3 years, while it would take approximately

1 week to cause erasure when exposed to the

direct sunlight. If the M2732A is to be exposed to

these types of lighting conditions for extended pe-

riods of time, it is suggested that opaque labels be

put over the M2732A window to prevent uninten-

tional erasure.

The recommended erasure procedure for the

M2732A is exposure to shortwave ultraviolet light

which has a wavelength of 2537 Å. The integrated

dose (i.e. UV intensity x exposure time) for erasure

should be a minimum of 15 W-sec/cm 2 . The era-

sure time with this dosage is approximately 15 to

20 minutes using an ultraviolet lamp with 12000

m W/cm 2 power rating. The M2732A should be

placed within 2.5 cm of the lamp tubes during

erasure. Some lamps have a filter on their tubes

which should be removed before erasure.

Table 3. Operating Modes

Mode

GV PP

V CC

Q0 - Q7

Read

V IL

V CC

Data Out

Program

V IL Pulse

V PP

V CC

Data In

Verify

V IL

V CC

Data Out

Program Inhibit

V IH

V PP

V CC

Hi-Z

Standby

V IH

V CC

Hi-Z

Note: X = V IH or V IL .

3/9

Programming

When delivered, and after each erasure, all bits of

the M2732A are in the “1" state. Data is introduced

by selectively programming ”0’s" into the desired

bit locations. Although only “0’s” will be pro-

grammed, both “1’s” and “0’s” can be presented in

the data word. The only way to change a “0" to a

”1" is by ultraviolet light erasure.

Th e M2732A is in the programming mode when the

GV PP input is at 21V. A 0.1

M2732A

AC MEASUREMENT CONDITIONS

Figure 4. AC Testing Load Circuit

20ns

Input Pulse Voltages 0.45V to 2.4V

Input and Output Timing Ref. Voltages 0.8V to 2.0V

1.3V

1N914

Note that Output Hi-Z is defined as the point where data

is no longer driven.

Figure 3. AC Testing Input Output Waveforms

3.3k

DEVICE

UNDER

TEST

OUT

2.4V

2.0V

C L = 100pF

0.45V

0.8V

AI00827

C L includes JIG capacitance

AI00828

Table 4. Capacitance (1) (T A = 25

C, f = 1 MHz )

Symbol

Parameter

Test Condition

Min

Max

Unit

C IN

Input Capacitance (except GV PP )

V IN = 0V

C IN1

Input Capacitance (GV PP )

V IN = 0V

C OUT

Output Capacitance

V OUT = 0V

Note: 1. Sampled only, not 100% tested.

Figure 5. Read Mode AC Waveforms

A0-A11

VALID

tAVQV

tAXQX

tGLQV

tEHQZ

tELQV

tGHQZ

Q0-Q7

DATA OUT

Hi-Z

AI00782

4/9

Input Rise and Fall Times

M2732A

Table 5. Read Mode DC Characteristics (1)

(T A = 0 to 70 ° C or –40 to 85 ° C; V CC = 5V ± 5% or 5V ± 10%; V PP = V CC )

Symbol

Parameter

Test Condition

Value

Unit

Min

Max

I LI

Input Leakage Current

V IN

V CC

I LO

Output Leakage Current

V OUT = V CC

I CC

Supply Current

E = V IL , G = V IL

125

I CC1

Supply Current (Standby)

E = V IH , G = V IL

V IL

Input Low Voltage

–0.1

0.8

V IH

Input High Voltage

V CC + 1

V OL

Output Low Voltage

I OL = 2.1mA

0.45

V OH

Output High Voltage

I OH = –400

2.4

Note: 1. V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP .

Table 6. Read Mode AC Characteristics (1)

(T A = 0 to 70

C or –40 to 85

C; V CC = 5V

5% or 5V

10%; V PP = V CC )

Test

Condition

M2732A

Symbol

Alt

Parameter

-2, -20 blank, -25 -3 -4

Min Max Min Max Min Max Min Max

Unit

t AVQV

t ACC

Address Valid to

Output Valid

E = V IL ,

G = V IL

200

250

300

450

t ELQV

t CE

Chip Enable Low to

Output Valid

G = V IL

200

250

300

450

t GLQV

t OE

Output Enable Low

to Output Valid

E = V IL

100

150

t EHQZ (2)

t DF

Chip Enable High to

Output Hi-Z

G = V IL

130

t GHQZ (2)

t DF

Output Enable High

to Output Hi-Z

E = V IL

130

t AXQX

t OH

Address Transition to

Output Transition

E = V IL ,

G = V IL

Notes: 1. V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP .

2. Sampled only, not 100% tested.

5/9

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