NSBMC096.PDF

August 1993

NSBMC096-16/-25/-33 Burst Memory Controller

General Description

The NSBMC096 Burst Memory Controller is an integrated

circuit which implements all aspects of DRAM control for

high performance systems using an i960 É CA/CF

SuperScalar Embedded Processor. The NSBMC096 is func-

tionally equivalent to the V96BMC TM .

The extremely high instruction rate achieved by these proc-

essors place extraordinary demands on memory system de-

sign if maximum throughput is to be sustained and costs

minimized.

Static RAM offers a simple solution for high speed memory

systems. However, high cost and low density make this an

expensive and space consumptive choice.

Dynamic RAMs are an attractive alternative with higher den-

sity and low cost. Their drawbacks are, slower access time

and more complex control circuitry required to operate

them.

The access time problem is solved if DRAMs are used in

page mode. In this mode, access times rival that of static

RAM. The control circuit problem is resolved by the

NSBMC096.

The function that the NSBMC096 performs is to optimally

translate the burst access protocol of the i960 CA/CF to the

page mode access protocol supported by dynamic RAMs.

The device manages one or two-way interleaved arrange-

ments of DRAMs such that during burst access, data can be

read, or written, at the rate of one word per system clock

cycle.

The NSBMC096 has been designed to allow maximum flexi-

bility in its application. The full range of processor speeds is

supported for a wide range of DRAM speeds, sizes and or-

ganizations.

No glue logic is required because the bus interface is cus-

tomized to the i960 CA/CF. System integration is further

enhanced by providing a 24-bit heartbeat timer and a bus

watch timer on-chip.

The NSBMC096 is packaged as a 132-pin PQFP with a foot-

print of only 1.3 square inches. It reduces design complexi-

ty, space requirements and is fully derated for loading, tem-

perature and voltage.

Features

Y Interfaces directly to the i960 CA

Y Integrated Page Cache Management

Y Manages Page Mode Dynamic Memory devices

Y On-chip Memory Address Multiplexer/Drivers

Y Supports DRAMs trom 256 kB to 64 MB

Y Bit counter/timer

Y Non-interleaved or two way interleaved operation

Y 5-Bit Bus Watch Timer

Y Software-configured operational parameters

Y High-Speed/Low Power CMOS technology

Block Diagram

TL/V/11805±1

This document contains information concerning a product that has been developed by National Semiconductor Corporation/V3 Corporation. This information

is intended to help in evaluating this product. National Semiconductor Corporation/V3 Corporation reserves the right to change and improve the specifications

of this product without notice.

TRI-STATE É is a registered trademark of National Semiconductor Corporation.

NSBMC096 TM and WATCHDOG TM are trademarks of National Semiconductor Corporation.

i960 É is a registered trademark of Intel Corporation.

V96BMC TM is a trademark of V3 Corporation.

C 1995 National Semiconductor Corporation

TL/V/11805

RRD-B30M115/Printed in U. S. A.

Logic and Connection Diagrams

TL/V/11805±2

TL/V/11805±3

Order Number NSBMC096VF

See Package Number VF132A

Pin Descriptions

TABLE I

Pin Ý Signal Name

91 V CC

92 V SS

93 AB4

94 AB5

95 AB6

96 AB7

97 V CC

98 V SS

99 AB8

100 AB9

101 AB10

102 AB11

103 V CC

104 V SS

105 CASB0

106 CASB1

107 CASB2

108 CASB3

109 V CC

110 V SS

111 RASB0

112 RASB1

113 RASB2

114 RASB3

115 V CC

118 MWEB

119 V SS

120 RESET

121 A2

122 A3

123 A4

124 A5

125 A6

126 A7

127 A8

128 A9

129 A10

130 A11

131 A12

132 A13

Note: In order for the switching characteristics of this device to be guaranteed, it is necessary to connect all of the power pins (V CC ,V SS ) to the appropriate power

levels. The use of low impedance wiring to the power pins is required. In systems using the i960 CA with its attendant high switching rates, multi-layer printed circuit

boards with buried power and ground planes are required.

Signal Name

Pin Ý

Signal Name

A14

LEB

A15

TXA

A16

TXB

V CC

A17

V SS

A19

AA0

A20

AA1

A18

AA2

A21

AA3

A24

V CC

A22

V SS

A23

AA4

A26

AA5

A25

AA6

A27

AA7

A31

V CC

A28

V SS

A29

AA8

A30

AA9

D/C

AA10

SUP

AA11

PCLK

V CC

INT

V SS

BERR

CASA0

W/R

CASA1

BE0

CASA2

DEN

CASA3

BLAST

V CC

BE1

V SS

RASA0

ADS

RASA1

BE2

RASA2

BE3

RASA3

BTERM

V CC

READY

MWEA

ID0

V SS

ID1

AB0

ID2

AB1

REFRESH

AB2

LEA

AB3

Pin Ý

Pin Descriptions (Continued)

i960 CA/CF INTERFACE

The following pins are functionally equivalent to those on

the i960 CA/CF from which their names are taken. Like

named pins on the i960 CA/CF and the NSBMC960 are to

be wired together. All 3-State outputs are to be weakly

pulled up to V CC . In typical situations, a 10 k X resistor is

sufficient.

Pin Description

A2±31 Address Bus (Input): This system bus is a word address which determines the location at which an access is

required.

ADS Address Strobe (Input; Active Low): Indicates that a new access cycle is being started.

D/*C Data/*Code (Input): Signals whether an access is for data or instructions.

BLAST Burst Last (Input; Active Low): Indicates that the last cycle of a burst is in progress.

DEN Data Enable (Input; Active Low): This input is monitored by the Bus Watch Timer to detect a bus access not

returning READY.

BTERM Burst Terminate (Output; 3-State; Active Low): This output is used to request termination of a burst in progress.

Used to disable burst writes.

READY Data Ready (Output; 3-State; Active Low): The READY output is used to signal that data on the processor bus is

valid for Read, or that data has been accepted for Write.

RESET Reset (Input; Active Low): Assertion of this input sets the NSBMC960 to its initial state. Following initialization, the

NSBMC960 must be configured before any memory access is possible.

BE0±3 Byte Enable (Input; Active Low): These inputs are used to determine which byte(s) within the addressed word are to

be accessed.

W/*R WRITE/*READ (Input): This input indicates the direction which data is to be transferred to/from on the data bus.

SUP Supervisor (Input; Active Low): Indicates that the processor is operating in supervisor mode. Required for access to

configuration registers.

PCLK System Clock (Input): Processor output clock required to operate and synchronize NSBMC960 internal functions.

BERR Bus Error (Output; Active Low): When enabled, this signal is generated by the Bus Watch Circuit to prevent

processor lock-up on access to a region that is not responding.

INT Interrupt (Output; 12 mA; Active Low): This signal is assented when the 24-bit counter reaches terminal count and

interrupt out is enabled. May be programmed for pulse or handshake operation.

ID0±2 Chip ID (Input): These inputs select the address offset of the NSBMC960 configuration registers. Each NSBMC960 in

a system must have a unique address for proper operation.

Pin Descriptions (Continued)

MEMORY INTERFACE

The NSBMC960 is designed to drive a memory array orga-

nized as 2 leaves each of 32 bits. The address and control

signals for the memory array are output through high current

drivers in order to minimize propagation delay due to input

impedance and trace capacitance. External array drivers

are not required. The address and control signals, however,

should be externally terminated.

Pin Description

A(A,B)0±11 Multiplexed Address Bus (Output; 24 mA): These two buses transfer the multiplexed row and column

addresses to the memory array leaves A and B. When non-interleaved operation is selected, only address bus A

should be used.

RAS(A,B)0±3 Row Address Strobes (Output; 12 mA Active Low): These strobes indicate the presence of a valid row

address on busses A(A,B)0±11. These signals are to be connected one to each leaf of memory. Four banks of

interleaved memory may be attached to a NSBMC960.

CAS(A,B)0±3 Column Address Strobe (Output; 12 mA, Active Low): These strobes latch a column address from A(A,B)0±

11. They are assigned one to each byte in a leaf.

MWE(A,B) Memory Write Enable (Output; 24 mA, Active Low): These are the DRAM write strobes. One is supplied for

each leaf to minimize signal loading.

REFRESH Refresh in progress (Output; 12 mA, Active Low): This output gives notice that a refresh cycle is to be

executed. The timing leads refresh RAS by one cycle.

BUFFER CONTROLS

Buffer control signals are provided to simplify the control of

the interface between the DRAM and i960 data busses.

Multiple operating modes facilitate choice of buffer type,

and simple bus buffers (``245''s), bus latches (``543''s) and

bus registers (``646''s) are all supported.

Description

TX(A,B)

Data Bus Transmit A and B (Output; Active Low): These outputs are multi-function signals. The signal names,

as they appear on the logic symbol, are the default signal names (Mode e 0). The purpose of these outputs is to

control buffer output enables during data read transactions and, in effect, control the multiplexing of data from

each memory leaf onto the i960 CA/CF data bus.

LE(A,B)

Data Bus Latch Enable A and B (Output; Active Low): These outputs are mode independent, however, the

timing of the signals change for different operational modes. They control transparent latches that hold data

transmiffed during a write transaction. In modes 0 and 1, the latch controls follow the timing of CAS for each

leaf, while in modes 2 and 3 the timing of LEA and LEB is shortened to (/2 clock.

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