l5_seql_verilog(1).pdf

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L5: Simple Sequential Circuits and Verilog
Verilog
Acknowledgements:
Materials in this lecture are courtesy of the following sources and are used with
permission.
Nathan Ickes
Rex Min
L5: 6.111 Spring 2006
Introductory Digital Systems Laboratory
1
L5: Simple Sequential Circuits and
 
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Key Points from L4 (Sequential Blocks)
Classification:
Latch: level sensitive (positive latch passes input to output on high phase, hold
value on low phase)
Register: edge-triggered (positive register samples input on rising edge)
Flip-Flop: any element that has two stable states. Quite often Flip-flop also used
denote an (edge-triggered) register
Positive
Latch
D
D
Q
Q
D
D
Q
Q
Positive
Register
Clk
Clk
Latches are used to build Registers (using the Master-Slave Configuration), but
are almost NEVER used by itself in a standard digital design flow.
Quite often, latches are inserted in the design by mistake (e.g., an error in your
Verilog code). Make sure you understand the difference between the two.
Several types of memory elements (SR, JK, T, D). We will most commonly use
the D-Register, though you should understand how the different types are built
and their functionality.
L5: 6.111 Spring 2006
Introductory Digital Systems Laboratory
2
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System Timing Parameters
In
D
Q
Combinational
Logic
D
Q
Clk
Clk
Register Timing Parameters
Logic Timing Parameters
T cq : worst case rising edge
clock to q delay
T cq, cd : contamination or
minimum delay from
clock to q
T su : setup time
T h : hold time
T logic : worst case delay
through the combinational
logic network
T logic,cd : contamination or
minimum delay
through logic network
L5: 6.111 Spring 2006
Introductory Digital Systems Laboratory
3
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System Timing (I): Minimum Period
CLout
In
D
Q
Combinational
Logic
D
Q
Clk
Clk
CLK
T h
T h
IN
T su
T su
T cq
T cq
FF1
T cq,cd
T logic
T cq,cd
CLout
T l,cd
T su2
T > T cq + T logic + T su
L5: 6.111 Spring 2006
Introductory Digital Systems Laboratory
4
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System Timing (II): Minimum Delay
CLout
In
D
Q
Combinational
Logic
D
Q
Clk
Clk
CLK
T h
T h
IN
T su
FF1
T cq,cd
CLout
T l,cd
T cq,cd + T logic,cd > T hold
L5: 6.111 Spring 2006
Introductory Digital Systems Laboratory
5
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