pcm1796.pdf

(711 KB) Pobierz
24-Bit 192-kHz Sampling Advanced-Segment Audio Stereo DAC (Rev. A
SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006
FEATURES
5-V Tolerant Digital Inputs
24-Bit Resolution
Small 28-Lead SSOP Package
Analog Performance:
− Dynamic Range: 123 dB
− THD+N: 0.0005%
APPLICATIONS
Differential Current Output: 4 mA p-p
SACD Players
8
Oversampling Digital Filter:
− Stop-Band Attenuation: –98 dB
− Pass-Band Ripple:
DVD Players
±
0.0002 dB
HDTV Receivers
Sampling Frequency: 10 kHz to 200 kHz
Car Audio Systems
System Clock: 128, 192, 256, 384, 512, or
768 f S With Autodetect
Digital Multitrack Recorders
Other Applications Requiring 24-Bit Audio
Accepts 16-, 20-, and 24-Bit Audio Data
PCM Data Formats: Standard, I 2 S, and
Left-Justified
DESCRIPTION
DSD Format Interface Available
The PCM1796 is a monolithic CMOS integrated circuit that
includes stereo digital-to-analog converters and support
circuitry in a small 28-lead SSOP package. The data
converters use TI’s advanced segment DAC architecture
to achieve excellent dynamic performance and improved
tolerance to clock jitter. The PCM1796 provides balanced
current outputs, allowing the user to optimize analog
performance externally. The PCM1796 accepts PCM and
DSD audio data formats, providing easy interfacing to
audio DSP and decoder chips. The PCM1796 also
interfaces with external digital filter devices (DF1704,
DF1706, PMD200). Sampling rates up to 200 kHz are
supported. A full set of user-programmable functions is
accessible through an SPI or I 2 C serial control port, which
supports register write and readback functions. The
PCM1796 also supports the time division multiplexed
command and audio (TDMCA) data format.
Interface Available for Optional External
Digital Filter or DSP
TDMCA or Serial Port (SPI/I 2 C)
User-Programmable Mode Controls:
− Digital Attenuation: 0 dB to –120 dB,
0.5 dB/Step
− Digital De-Emphasis
− Digital Filter Rolloff: Sharp or Slow
− Soft Mute
− Zero Flag for Each Output
Compatible With PCM1792 (Pins and Mode
Controls)
Dual Supply Operation:
− 5-V Analog, 3.3-V Digital
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2006, Texas Instruments Incorporated
A/V Receivers
×
154426529.039.png 154426529.040.png 154426529.041.png 154426529.042.png 154426529.001.png 154426529.002.png 154426529.003.png 154426529.004.png 154426529.005.png 154426529.006.png 154426529.007.png 154426529.008.png 154426529.009.png 154426529.010.png 154426529.011.png 154426529.012.png 154426529.013.png 154426529.014.png 154426529.015.png 154426529.016.png 154426529.017.png 154426529.018.png 154426529.019.png 154426529.020.png 154426529.021.png 154426529.022.png 154426529.023.png
www.ti.com
SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006
ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE CODE
OPERATION
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PCM1796DB
28-lead SSOP
28DB
–25 ° C to 85 ° C
PCM1796
PCM1796DB
Tube
PCM1796DBR
Tape and reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
PCM1796
Supply voltage
V CC 1, V CC 2L, V CC 2R
–0.3 V to 6.5 V
V DD
–0.3 V to 4 V
Supply voltage differences: V CC 1, V CC 2L, V CC 2R
± 0.1 V
Ground voltage differences: AGND1, AGND2, AGND 3L, AGND 3R, DGND
±
0.1 V
Digital input
voltage
LRCK, DATA, BCK, SCK, MSEL, RST , MS (2) , MDI, MC, MDO (2) , ZEROL (2) , ZEROR (2)
–0.3 V to 6.5 V
ZEROL (3) , ZEROR (3) , MDO (3) , MS (3)
–0.3 V to (V DD + 0.3 V) < 4 V
Analog input voltage
–0.3 V to (V CC + 0.3 V) < 6.5 V
Input current (any pins except supplies)
± 10 mA
Ambient temperature under bias
–40 ° C to 125 ° C
Storage temperature
–55 ° C to 150 ° C
Junction temperature
150 ° C
Lead temperature (soldering)
260
°
C, 5 s
C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input mode or I 2 C mode
(3) Output mode except for I 2 C mode
ELECTRICAL CHARACTERISTICS
all specifications at T A = 25 ° C, V CC 1 = V CC 2L = V CC 2R = 5 V, V DD = 3.3 V, f S = 44.1 kHz, system clock = 256 f S , and 24-bit data unless
otherwise noted
Package temperature (IR reflow, peak)
260
°
PARAMETER
TEST CONDITIONS
PCM1796DB
UNIT
MIN
TYP
MAX
RESOLUTION
24
Bits
DATA FORMAT (PCM Mode)
Audio data interface format
Standard, I 2 S, left-justified
Audio data bit length
16-, 20-, 24-bit selectable
Audio data format
MSB first, twos complement
f S
Sampling frequency
10
200
kHz
System clock frequency
128, 192, 256, 384, 512, 768 f S
DATA FORMAT (DSD Mode)
Audio data interface format
DSD (direct stream digital)
Audio data bit length
1 Bit
f S
Sampling frequency
2.8224
MHz
System clock frequency
2.8224
11.2896
MHz
2
PCM1796DB
28-lead SSOP
28DB
–25 ° C to 85 ° C
PCM1796
Supply voltage
Digital input
PARAMETER
TEST CONDITIONS
UNIT
154426529.024.png
www.ti.com
SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at T A = 25
°
C, V CC 1 = V CC 2L = V CC 2R = 5 V, V DD = 3.3 V, f S = 44.1 kHz, system clock = 256 f S , and 24-bit data unless
otherwise noted
PARAMETER
TEST CONDITIONS
PCM1796DB
UNIT
MIN
TYP
MAX
DIGITAL INPUT/OUTPUT
Logic family
TTL compatible
V IH
Input logic level
2
VDC
V IL
0.8
I IH
Input logic current
V IN = V DD
10
µ A
I IL
V IN = 0 V
–10
V OH
Output logic level
I OH = –2 mA
2.4
VDC
V OL
I OL = 2 mA
0.4
DYNAMIC PERFORMANCE (PCM MODE) (1)(2)
f S = 44.1 kHz
0.0005%
0.001%
THD+N at V OUT = 0 dB
f S = 96 kHz
0.001%
f S = 192 kHz
0.0015%
EIAJ, A-weighted, f S = 44.1 kHz
120
123
Dynamic range
EIAJ, A-weighted, f S = 96 kHz
123
dB
EIAJ, A-weighted, f S = 192 kHz
123
EIAJ, A-weighted, f S = 44.1 kHz
120
123
Signal-to-noise ratio
EIAJ, A-weighted, f S = 96 kHz
123
dB
EIAJ, A-weighted, f S = 192 kHz
123
f S = 44.1 kHz
116
119
Channel separation
f S = 96 kHz
118
dB
f S = 192 kHz
117
Level Linearity Error
V OUT = –120 dB
± 1
dB
DYNAMIC PERFORMANCE (MONO MODE) (1)(2)(3)
f S = 44.1 kHz
0.0005%
THD+N at V OUT = 0 dB
f S = 96 kHz
0.001%
f S = 192 kHz
0.0015%
EIAJ, A-weighted, f S = 44.1 kHz
126
Dynamic range
EIAJ, A-weighted, f S = 96 kHz
126
dB
EIAJ, A-weighted, f S = 192 kHz
126
EIAJ, A-weighted, f S = 44.1 kHz
126
Signal-to-noise ratio
EIAJ, A-weighted, f S = 96 kHz
126
dB
EIAJ, A-weighted, f S = 192 kHz
126
(1) Filter condition:
THD+N: 20-Hz HPF, 20-kHz AES17 LPF
Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Channel separation: 20-Hz HPF, 20-kHz AES17 LPF
Analog performance specifications are measured using the System Two Cascade audio measurement system by Audio Precision in the
averaging mode.
(2) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 36.
(3) Dynamic performance and dc accuracy are specified at the output of the measurement circuit as shown in Figure 38.
Audio Precision and System Two are trademarks of Audio Precision, Inc.
Other trademarks are the property of their respective owners.
3
PARAMETER
TEST CONDITIONS
UNIT
Input logic level
VDC
Input logic current
µ A
Output logic level
VDC
THD+N at V OUT = 0 dB
Dynamic range
dB
Signal-to-noise ratio
dB
Channel separation
dB
THD+N at V OUT = 0 dB
Dynamic range
dB
Signal-to-noise ratio
dB
154426529.025.png 154426529.026.png 154426529.027.png 154426529.028.png
www.ti.com
SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at T A = 25
°
C, V CC 1 = V CC 2L = V CC 2R = 5 V, V DD = 3.3 V, f S = 44.1 kHz, system clock = 256 f S , and 24-bit data unless
otherwise noted
PARAMETER
TEST CONDITIONS
PCM1796DB
UNIT
MIN
TYP
MAX
DSD MODE DYNAMIC PERFORMANCE (1) (2) (44.1 kHZ, 64 f S )
THD+N at FS
2 V rms
0.0007%
Dynamic range
–60 dB, EIAJ, A-weighted
122
dB
Signal-to-noise ratio
EIAJ, A-weighted
122
dB
ANALOG OUTPUT
Gain error
–7
± 2
7 % of FSR
Gain mismatch, channel-to-channel
–3
±
0.5
3 % of FSR
Bipolar zero error
At BPZ
–2
± 0.5
2 % of FSR
Output current
Full scale (0 dB)
4
mA p-p
Center current
At BPZ
–3.5
mA
DIGITAL FILTER PERFORMANCE
De-emphasis error
±
0.1
dB
FILTER CHARACTERISTICS–1: SHARP ROLLOFF
Pass band
± 0.0002 dB
0.454 f S
–3 dB
0.49 f S
Stop band
0.546 f S
Pass-band ripple
± 0.0002
dB
Stop-band attenuation
Stop band = 0.546 f S
–98
dB
Delay time
38/f S
s
FILTER CHARACTERISTICS–2: SLOW ROLLOFF
Pass band
± 0.001 dB
0.21 f S
–3 dB
0.448 f S
Stop band
0.79 f S
Pass-band ripple
±
0.001
dB
Stop-band attenuation
Stop band = 0.732 f S
–80
dB
Delay time
38/f S
s
(1) Filter condition:
THD+N: 20-Hz HPF, 20-kHz AES17 LPF
Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Channel separation: 20-Hz HPF, 20-kHz AES17 LPF
Analog performance specifications are measured using the System Two Cascade audio measurement system by Audio Precision in the averaging
mode.
(2) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 37.
4
PARAMETER
TEST CONDITIONS
UNIT
Pass band
Pass band
154426529.029.png 154426529.030.png 154426529.031.png 154426529.032.png 154426529.033.png
www.ti.com
SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at T A = 25
°
C, V CC 1 = V CC 2L = V CC 2R = 5 V, V DD = 3.3 V, f S = 44.1 kHz, system clock = 256 f S , and 24-bit data unless
otherwise noted
PARAMETER
TEST CONDITIONS
PCM1796DB
UNIT
MIN
TYP
MAX
POWER SUPPLY REQUIREMENTS
V DD
3
3.3
3.6
VDC
V CC 1
Voltage range
V CC 2L
4.75
5
5.25
VDC
V CC 2R
f S = 44.1 kHz
7
9
I DD
f S = 96 kHz
13
mA
Supply current (1)
f S = 192 kHz
25
f S = 44.1 kHz
18
23
I CC
f S = 96 kHz
19
mA
f S = 192 kHz
20
f S = 44.1 kHz
115
150
Power dissipation (1)
f S = 96 kHz
140
mW
f S = 192 kHz
180
TEMPERATURE RANGE
Operation temperature
–25
85
° C
θ JA
Thermal resistance
28-pin SSOP
100
°
C/W
(1) Input is BPZ data.
PIN ASSIGNMENTS
PCM1796
(TOP VIEW)
ZEROL
ZEROR
MSEL
LRCK
DATA
BCK
SCK
DGND
V DD
MS
MDI
MC
MDO
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V CC 2L
AGND3L
I OUT L–
I OUT L+
AGND2
V CC 1
V COM L
V COM R
I REF
AGND1
I OUT R–
I OUT R+
AGND3R
V CC 2R
5
PARAMETER
TEST CONDITIONS
UNIT
Voltage range
I DD
mA
Supply current (1)
I CC
mA
Power dissipation (1)
mW
154426529.034.png 154426529.035.png 154426529.036.png 154426529.037.png 154426529.038.png

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin