DS12887A.pdf

www.maxim-ic.com

DS12887A

Real-Time Clock

www.maxim-ic.com

FEATURES

PIN ASSIGNMENT (Top View)

Drop-in replacement for IBM AT computer

clock/calendar

MOT

V CC

SQW

Pin compatible with the MC146818B and

DS1287A

N.C.

AD0

Totally nonvolatile with over 10 years of

operation in the absence of power

RCLR

AD1

N.C.

IRQ

RESET

N.C.

R/W

AD2

Counts seconds, minutes, hours, days, day of

the week, date, month, and year with leap-

year compensation valid up to 2100

AD3

AD4

AD5

AD6

AD7

GND

Binary or BCD representation of time,

calendar, and alarm

DS12887A

24 PDIP Module (700mil)

12-hour or 24-hour clock with AM and PM

in 12-hour mode

Package Dimension Information

http://www.maxim-ic.com/TechSupport/DallasPackInfo.htm

Daylight Savings Time option

Selectable between Motorola and Intel bus

timing

Multiplex bus for pin efficiency

PIN DESCRIPTION

AD0–AD7 - Multiplexed Address/Data Bus

N.C.

Interfaced with software as 128 RAM

locations

– 14 bytes of clock and control registers

– 114 bytes of general-purpose RAM

- No Connect

M OT

- Bus Type Selection

- RTC Chip-Select Input

Programmable square-wave output signal

A S

- Address Strobe

R/ W

- Read/Write Input

Bus-compatible interrupt signals (IRQ)

- Data Strobe

Three interrupts are separately software-

maskable and testable

– Time-of-day alarm once/second to

once/day

– Periodic rates from 122

RES ET

- Reset Input

IRQ

- Interrupt Request Output

SQW

- Square-Wave Output

s to 500ms

– End-of-clock update cycle

V CC

- +5V Main Supply

RCLR

- RAM Clear

Underwriters Laboratory (UL) recognized

GND

- Ground

ORDERING INFORMATION

PART PIN-PACKAGE TOP MARK TEMP RANGE

DS12887A 24 PDIP Module

DS12887A

0°C to +70°C

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here: http://www.maxim-ic.com/errata .

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073102

Self-contained subsystem includes lithium,

quartz, and support circuitry

DS12887A

DESCRIPTION

The DS12887A real-time clock plus RAM is designed to be a direct replacement for the DS1287A. The

DS12887A is identical in form, fit, and function to the DS1287A, and includes additional 64 bytes of

general-purpose RAM. Access to this additional RAM sp ace is determined by the logic level presented on

AD6 during the address portion of an access cycle. The RCLR pin is used to clear (set to logic 1) all 114

bytes of general-pu rpose RAM but does not affect the RAM associated with the real-time clock. In order

to clear the RAM, RCLR must be force d to an input logic 0 (-0.3V to +0.8V) during battery-backup mode

when V CC is not applied. The RCLR function is designed to be used by human interface (shorting to

ground manually or by switch) and not to be driven with external buffers.

For a complete descr iption of operating conditions, electrical characteristics, bus timing and pin

descriptions other than RCLR , refer to the DS12887 data sheet.

Note: Pins 2, 3, 16, 20, and 22 are missing by design. This device cannot be stored or shipped in conductive material that will give a continuity

path between the RAM clear pin and ground.

TYPICAL OPERATING CIRCUIT

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